Semiconductor memory defect analysis method and defect analysis system

A defect analysis method for semiconductor memory comprising:

• selecting a memory macro to be analyzed from a semiconductor device having a large number of memory macros mounted on one chip, and inputting an address bit map of the selected memory macro;
• inputting size information of the memory macro;
• translating a logical address of a defective cell of the memory macro detected on the basis of results of an electric test measured by using a tester to a physical address of a memory macro in a standard disposition by using the input size information and the input address bit map of the memory macro, and generating a fail bit map in the standard disposition;
• inputting disposition information of the memory macro;
• and
• translating a physical address of the fail bit map in the standard disposition to a physical address of the memory macro by using the input disposition information of the memory macro, and generating a fail bit map of the memory macro.

A defect analysis system for semiconductor memory comprising:

• an input unit configured to select a memory macro to be analyzed from a semiconductor device having a large number of memory macros mounted on one chip, and configured to input a kind of the selected memory macro, size information of the memory macro and disposition information of the memory macro;
• a readout unit configured to read out an address bit map corresponding to the input kind of the memory macro from a database which stores address bit maps respectively corresponding to memory macro kinds;
• a standard disposition address translation unit configured to translate a logical address of a defective cell of the memory macro detected on the basis of results of an electric test measured by using a tester to a physical address of a memory macro in a standard disposition by using the input size information and the address bit map read out, of the memory macro, and configured to generate a fail bit map in the standard disposition;
• and
• a fail bit map generation unit configured to translate a physical address of the fail bit map in the standard disposition to a physical address of the memory macro by using the input disposition information of the memory macro, and configured to generate a fail bit map of the memory macro.

A defect analysis system for semiconductor memory comprising:

• an input unit configured to select a memory macro to be analyzed from a semiconductor device having a large number of memory macros mounted on one chip, and configured to input an address bit map of the selected memory macro, size information of the memory macro, and disposition information of the memory macro;
• a standard disposition address translation unit configured to translate a logical address of a defective cell of the memory macro detected on the basis of results of an electric test measured by using a tester to a physical address of a memory macro in a standard disposition by using the input size information and the input address bit map of the memory macro, and configured to generate a fail bit map in the standard disposition;
• and
• a fail bit map generation unit configured to translate a physical address of the fail bit map in the standard disposition to a physical address of the memory macro by using the input disposition information of the memory macro, and configured to generate a fail bit map of the memory macro.