Performance Analysis Based System Level Power Management

A multiprocessor system-on-chip (SoC) with dynamic adaptive power management for execution of data-dependent applications, characterized by:

• a plurality of performance counters with individual ones disposed in each processor each periphera, and an interconnecting internal system bus of a multiprocessor system implemented in a system-on-chip;
• a resource requirements table that maps the performance levels required for a scheduled resource by a task in an application;
• power manager for controlling at least one of DVS, DFS, and timeout to respective system resources associated with each of the performance counters, and that during run-time consults the resource requirements table for appropriate power management settings;
• a static process for pre-loading the resource requirements table with performance requirements for a list of known applications and uses;
• and a dynamic process for updating entries in the resource requirements table with performance requirements that have been extracted during run-time from data collected from the plurality performance c wherein, the power manager issues such controls as are necessary to optimize power at the system-level and such controls are dynamic and adaptive to changing conditions in the application that cannot be predicted before run-time.