Memory Security Device
AssigneeKabushiki Kaisha Toshiba
InventorSeiichiro Saito
Life of this patent
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Abstract
Embodiments of the systems and methods presented herein may provide memory security in a semiconductor device or a computing system using an address encryption section operable to encrypt a write address or a read address, a data encrypting section operable to encrypt data to be written, a write section operable to write encrypted data at an encrypted write address corresponding to a memory, a read section operable to read encrypted data from the encrypted read address corresponding to the memory and a data decryption section operable to decrypt the read encrypted data to obtain read data corresponding to the read address.
Claims20
A semiconductor device having a memory security block, the memory security block comprising:
- an address encryption section operable to encrypt a write address or a read address;
- a data encrypting section operable to encrypt data to be written;
- a write section operable to write encrypted data at an encrypted write address corresponding to a memory;
- a read section operable to read encrypted data from the encrypted read address corresponding to the memory;
- and
- a data decryption section operable to decrypt the read encrypted data to obtain read data corresponding to the read address.
A method of protecting the contents of a memory, comprising:
- if data is to be written:
- encrypting a write address corresponding to a memory;
- encrypting the data to be written;
- and
- writing the encrypted data at the encrypted write address in the memory;
- and
- if data is to be read:
- encrypting a read address corresponding to the memory;
- reading the encrypted data from the encrypted read address corresponding to the memory;
- and
- decrypting the read encrypted data to obtain read data corresponding to the read address.
A computer system for use with digital television, comprising:
- a multi-processor unit operable to decode compressed first data, generate second data from the first data and encode the second data to generate compressed second data;
- a memory/processor controller operable to receive third data and store the third data in a first memory, the memory/processor controller having a memory security block, the memory security block comprising:
- an address encryption section operable to encrypt a write address or a read address;
- a data encrypting section operable to encrypt data to be written;
- a write section operable to write encrypted data at an encrypted write address corresponding to the first memory;
- a read section operable to read encrypted data from the encrypted read address corresponding to the first memory;
- and
- a data decryption section operable to decrypt the read encrypted data to obtain read data corresponding to the read address;
- a central processing unit coupled to the memory/processor controller;
- and
- an I/O unit coupled to one or more devices and operable to receive data from the one or more devices, a multi-processor unit and a memory/processor controller and communicate data to the one or more devices, the multi-processor unit and the memory/processor controller.
Dependencies are inferred from the claim text.