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AssigneeAxis Semiconductor, Inc.
InventorXiaolin Wang
Estimating the term…
A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured by software for each specific application by communication through a switch fabric in a dynamic, parallel and flexible fashion to achieve a reconfigurable pipeline, wherein the length of the pipeline stages and the order of the stages varies from time to time and from application to application, admirably handling the explosion of varieties of diverse signal processing needs in single devices such as handsets, set-top boxes and the like with unprecedented performance, cost and power savings, and with full application flexibility.
A flexible data pipeline architecture for accommodating substantially all types of software computational instruction sets for varying applications having, in combination, a programmable embedded processor with reconfigurable pipeline stages the order and lengths of which vary in response to varying application instruction sets that establish corresponding configurations of the processor and of the connections amongst its functional components specifically to suit the application.
A flexible data pipeline structure for accommodating software computational instructions for varying program applications, having, in combination, a programmable embedded processor with reconfigurable pipeline stages the order and length of which varies in response to varying program application instructions;
A method of processing computer software computational instructions fed to a processor, that comprises, compiling and analyzing inputted user software applications to determine the specific computational tasks that need to be performed for each software application;
A method of signal processing combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured by software to each specific application by communication through a switch fabric in a dynamic, parallel and flexible fashion to achieve a reconfigurable pipeline wherein the length of the pipeline stages and the order of the stages are varied from time to time and from application to application, handling the adapting to the explosion of varieties of diverse signal processing needs in single devices such as handsets, set-top boxes and the like.
Dependencies are inferred from the claim text.