Scheduling threads in a processor

A mobile terminal comprising a processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of said instructions defining a memory access operation, comprising:

• a plurality of instruction buffers, each for holding at least one instruction of a thread associated with that buffer;
• an instruction issue stage for issuing instructions from the instruction buffers;
• a memory access stage connected to a memory and arranged to receive instructions issued by the instruction issue stage;
• said memory access stage comprising:
• detecting logic adapted to detect whether a memory access operation is defined in each issued instruction;
• and
• instruction fetch logic adapted to instigate an instruction fetch to fetch an instruction of a thread when no memory access operation is detected.

An array of processors, each processor comprising a processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of said instructions defining a memory access operation, comprising:

• a plurality of instruction buffers, each for holding at least one instruction of a thread associated with that buffer;
• an instruction issue stage for issuing instructions from the instruction buffers;
• a memory access stage connected to a memory and arranged to receive instructions issued by the instruction issue stage;
• said memory access stage comprising:
• detecting logic adapted to detect whether a memory access operation is defined in each issued instruction;
• and
• instruction fetch logic adapted to instigate an instruction fetch to fetch an instruction of a thread when no memory access operation is detected.

A method of executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of said instructions defining a memory access operation, the method comprising:

• holding at least one instruction of a thread in an instruction buffer for that thread;
• issuing instructions from the instruction buffers to an instruction issue stage of an execution pipeline;
• receiving instructions issued by the instruction issue stage at a memory access stage connected to a memory;
• detecting whether a memory access operation is defined in the instruction and, when it is not, instigating an instruction fetch operation to fetch an instruction of a thread.

A processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of said instructions defining a memory access operation, comprising:

• buffer means for holding instructions of threads;
• instruction issue means for issuing instructions from the buffer means;
• memory access means connected to a memory and arranged to receive instructions issued by the instruction issue means;
• said memory access means comprising:
• means for detecting whether a memory access operation is defined in each issued instruction;
• and
• means for instigating an instruction fetch to fetch an instruction of a thread when no memory access operation is detected.