US 2008/0301408 A1 · SYSTEM COMPRISING A PLURALITY OF PROCESSORS AND METHOD OF OPERATING THE SAME

Abstract

A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables.

Claims20

Dependent claims

A system comprising a master processor and at least one slave processor, wherein a state of said master processor comprises a first plurality of variables and a state of said slave processor comprises a second plurality of variables, said system comprising a parallel mode of operation wherein data are processed by said master processor and said slave processor and a serial mode of operation wherein data are processed by said master processor;

said system being configured to perform, in case of an interrupt or exception occurring in said parallel mode of operation, the steps of saving at least a portion of said first plurality of variables and said second plurality of variables to a buffer memory and switching said system to said serial mode of operation;
said system further being configured to set at least one of said first plurality of variables to a value of at least one of said second plurality of variables in case said interrupt or exception is occurring in said slave processor.

A system comprising a master processor and at least one slave processor, wherein a state of said master processor comprises a first plurality of variables comprising a first return address and a state of said slave processor comprises a second plurality of variables comprising a second return address, said system comprising a parallel mode of operation wherein data are processed by said master processor and said slave processor and a serial mode of operation wherein data are processed by said master processor;

wherein said system comprises a trampoline instruction;
said system being configured to perform, in case of an interrupt or exception occurring in said master processor during said parallel mode of operation, the steps of saving said first return address and said second plurality of variables to a buffer memory, replacing said first return address with an address of said trampoline instruction and switching to said serial mode of operation;
said system further being configured to perform, in case of an interrupt or exception occurring in said slave processor during said parallel mode of operation, the steps of saving said first plurality of variables and said second plurality of variables to a buffer memory, setting at least one of said first plurality of variables to a value of at least one of said second plurality of variables, replacing said first return address with an address of said trampoline instruction and switching to said first mode of operation;
wherein said trampoline instruction is adapted to perform the steps of switching said system to said parallel mode of operation and reading said second plurality of variables and said first return address from said buffer memory if said interrupt or exception occurred in said master processor;
and
wherein said trampoline instruction is adapted to perform the steps of switching said system to said parallel mode of operation, reading said second plurality of variables from said buffer memory, setting said at least one of said second plurality of variables to a value of said at least one of said first plurality of variables and reading said first plurality of variables from said buffer memory if said interrupt or exception occurred in said at least one slave processor.

3 more elements

A method of operating a system comprising a master processor and at least one slave processor, a state of said master processor comprising a first plurality of variables and a state of said slave processor comprising a second plurality of variables, said system comprising a parallel mode of operation wherein data are processed by said master processor and said slave processor and a serial mode of operation wherein data are processed by said slave processor, said method comprising:

performing, in case of an interrupt or exception occurring in said parallel mode of operation, the steps of saving at least a portion of said first plurality of variables and said second plurality of variables to a buffer memory and switching said system to said serial mode of operation;
and
setting at least one of said first plurality of variables to a value of at least one of said second plurality of variables in case said interrupt or exception is occurring in said at least one slave processor.

Dependencies are inferred from the claim text.

System comprising a plurality of processors and method of operating the same

Life of this patent

System comprising a plurality of processors and method of operating the same

Life of this patent

Abstract

Claims20