Method, Apparatus, and System Supporting Improved DMA Writes

A memory controller for a data processing system including a memory subsystem, said memory controller comprising:

• a memory interface coupled to the memory subsystem;
• an Input/Output (I/O) interface including an I/O queue from which DMA write operations are performed in First-In First-Out (FIFO) order, wherein the I/O interface receives a stream of multiple direct memory access (DMA) write operations and enqueues the multiple DMA write operations in the I/O queue;
• and
• a coherency unit including a coherence directory, wherein the coherency unit, prior to processing of a particular DMA write operation enqueued within the queue according to the FIFO order, acquires coherency ownership of a target memory block specified by the particular DMA write operation and, in response to acquiring coherency ownership of the target memory block, updates an entry in a lower latency second array to a particular coherency state signifying coherency ownership of the target memory block by the memory controller, and wherein responsive to the particular DMA write operation being a next DMA write operation in the stream to be performed according to the FIFO order, the coherency unit accesses both a higher latency first array and the lower latency second array, and if the lower latency second array indicates the particular coherency state, signals, prior to results being obtained from the higher latency first array, that the particular DMA write operation can be performed;
• wherein the memory controller, in response to the signaling, performs an update to the memory subsystem indicated by the particular DMA write operation.

A data processing system, comprising:

• multiple processors each having a respective associated cache memory;
• a memory subsystem;
• and
• a memory controller coupled to the multiple processors and the memory subsystem, said memory controller including:
• a memory interface coupled to the memory subsystem;
• an Input/Output (I/O) interface including an I/O queue from which DMA write operations are performed in First-In First-Out (FIFO) order, wherein the I/O interface receives a stream of multiple direct memory access (DMA) write operations and enqueues the multiple DMA write operations in the I/O queue;
• and
• a coherency unit including a coherence directory, wherein the coherency unit, prior to processing of a particular DMA write operation enqueued within the queue according to the FIFO order, acquires coherency ownership of a target memory block specified by the particular DMA write operation and, in response to acquiring coherency ownership of the target memory block, updates an entry in higher latency first array and a lower latency second array to a particular coherency state signifying coherency ownership of the target memory block by the memory controller, and wherein responsive to the particular DMA write operation being a next DMA write operation in the stream to be performed according to the FIFO order, the coherency unit accesses both the higher latency first array and the lower latency second array, and if the lower latency second array indicates the particular coherency state, signals, prior to results being obtained from the higher latency first array, that the particular DMA write operation can be performed;
• wherein the memory controller, in response to the signaling, performs an update to the memory subsystem indicated by the particular DMA write operation.