Structure for dynamic livelock resolution with variable delay memory access queue

A design structure embodied in a machine readable medium for designing, manufacturing, or testing a livelock detection mechanism, the design structure comprising:

• a processor load queue for issuing load requests;
• a delay queue, which comprises a delay path including (a) a plurality of initial delay stages including a first stage and associated first staging multiplexer (MUX), (b) a final stage with an associated final staging MUX;
• a feedback path for returning retried operations as an input to the first staging MUX;
• at least one bypass path extending from before one of the plurality of initial delay stages to an input of the final staging MUX;
• a memory subsystem controller for controlling access to a memory subsystem;
• a livelock detection mechanism that monitors for the occurrence of a livelock condition within the system;
• and
• a delay queue controller having livelock resolution logic that is activated by the livelock detection mechanism, wherein said delay queue controller responds to the detection of the livelock condition by dynamically changing a selection at said final staging MUX to enable rescheduling of a retried operation ahead of a newer operation at the memory subsystem controller;
• wherein, when the livelock condition is resolved, said delay queue controller triggers a selection of operations on the bypass path at the final staging MUX.

A method in a computer aided design system for generating a functional design model of a circuit, the method comprising:

• generating a functional computer-simulated representation of a mechanism for detecting the presence of a livelock condition in a data processing system having a memory subsystem controller and a processor with:
• a delay queue with a series of initial delay stages;
• a final stage with a final stage multiplexer (MUX);
• a feedback path;
• one or more bypass paths;
• and livelock detection and resolution logic;
• generating a functional computer-simulated representation of a mechanism for determining whether the livelock condition is a first type livelock condition or a second type livelock condition;
• generating a functional computer-simulated representation of a mechanism for, when the livelock condition is a first type livelock condition, dynamically triggering a delay queue controller to implement a first response for resolving the livelock condition, wherein said first response includes selecting at the final stage MUX an input of a retried instruction ahead of a next input of a subsequent instruction and automatically directing a transmission of each new instruction to the memory subsystem controller via a delay path rather than via a bypass path such that the retried instruction is presented to the memory controller ahead of the subsequent and new instructions.