Data transfer control device and electronic instrument
AssigneeSeiko Epson Corporation
InventorHiroyasu Honda
Life of this patent
Estimating the term…
Abstract
A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates an interface signal and outputs the generated interface signal to an interface bus; and an internal register in which is set timing information for specifying a timing at which a signal level of the interface signal output from the interface circuit changes. The interface circuit generates the interface signal, a signal level of which changes at a timing according to the timing information set in the internal register.
Claims11
A data transfer control device which controls data transfer, the data transfer control device being configured such that:
- the data transfer control device analyzes a first packet transferred from a host-side data transfer control device to the data transfer control device through a serial bus;
- the data transfer control device generates signals and outputs the interface signal to an interface bus;
- and
- the data transfer control device includes an internal register that stores timing information according to the first packet for specifying a timing at which a signal level of a signal the signals changes, the timing information being set based on the first packet.
A host-side data transfer control device which controls data transfer to a target-side data transfer control device, the host-side data transfer control device being configured such that:
- the host-side data transfer control device performs interfacing to a host system device;
- the host-side data transfer control device generates a packet to be transmitted to a target-side data transfer control device through a serial bus;
- the host-side data transfer control device including an internal register accessed by the host system, the internal register stores timing information for specifying a timing at which a signal level of an interface signal changes, the interface signal being outputted from the target-side data transfer control device;
- and
- the host-side data transfer control device generates the packet including the timing information set in the internal register, and transmits the generated packet to the target-side data transfer control device through the serial bus.
An electronic instrument, comprising:
- a target side data transfer control device being configured such that:
- the data transfer control device analyzes a first packet transferred from a host-side data transfer control device to the data transfer control device through a serial bus;
- the data transfer control device generates signals and outputs the interface signal to an interface bus;
- and
- the data transfer control device including an internal register that stores timing information according to the first packet for specifying a timing at which a signal level of a signal the signals changes, the timing information being set based on the first packet;
- a host-side data transfer control device connected with the target-side data transfer control device through the serial bus, the host-side data transfer control device being configured such that:
- the host-side data transfer control device performs interfacing to a host system device;
- the host-side data transfer control device generates a packet to be transmitted to a target-side data transfer control device through a serial bus;
- the host-side data transfer control device including an internal register accessed by the host system, the internal register stores timing information for specifying a timing at which a signal level of an interface signal changes, the interface signal being outputted from the target-side data transfer control device;
- and
- the host-side data transfer control device generates the packet including the timing information set in the internal register, and transmits the generated packet to the target-side data transfer control device through the serial bus;
- and
- at least one device connected to the target-side data transfer control device through the interface bus.
Dependencies are inferred from the claim text.