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US 2008/0293246 A1Published application
Vertical fet with nanowire channels and a silicided bottom contact
AssigneeInternational Business Machines Corporation
InventorsGuy Moshe Cohen, Paul M. Solomon
Life of this patent
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Abstract
A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.
Claims7
A method of forming a semiconductor structure comprising:
- forming a silicide contact layer on, or within, a specified region of a semiconductor substrate;
- forming nanowires from a plurality of catalyst dots that are formed over said silicide contact layer;
- depositing a gate dielectric and a gate conductor over said nanowires;
- planarizing said nanowires to trim said nanowires to be of same length;
- recessing the gate conductor and forming insulator plugs over said recessed gate conductor;
- and
- forming contacts to an upper surface of each of said nanowires, to said silicide contact layer and to said gate conductor.
4 more elements
A method of forming a semiconductor structure comprising:
- forming a silicide contact layer on, or within, a specified region of a semiconductor substrate;
- forming nanowires from a plurality of catalyst dots that are formed over said silicide contact layer;
- depositing a gate dielectric and a filling material over said nanowires;
- planarizing said nanowires to trim said nanowires to be of same length;
- removing the filling material and forming a recessed gate conductor in the space previously including the filling material;
- forming insulator plugs over said recessed gate conductor;
- and
- forming contacts to an upper surface of each of said nanowires, to said silicide contact layer and to said gate conductor.
5 more elements
Dependencies are inferred from the claim text.