US 2008/0293195 A1 · GATE STRAINING IN A SEMICONDUCTOR DEVICE

Abstract

Gate straining techniques as described herein can be utilized during the fabrication of NMOS transistor devices, PMOS transistor devices, or CMOS device structures. For an NMOS device, conductive vias are formed in TEOS oxide regions surrounding the sidewall spacers of a metal gate structure, where the metal gate structure includes compressive nitride material within the gate opening. After forming the conductive vias the remaining TEOS oxide is removed and tensile nitride material is deposited between the sidewall spacers and the conductive vias. The sidewall spacers serve as retaining walls for the tensile nitride material, which preserves the tensile characteristics of the material. A similar fabrication technique is utilized to form a PMOS device. For a PMOS device, however, the metal gate structure includes tensile nitride material within the gate opening, and compressive nitride material between the sidewall spacers and the conductive vias.

Claims21

Dependent claims

A method of fabricating a semiconductor device, the method comprising:

providing a device structure on a semiconductor substrate, the device structure comprising a first spacer, a second spacer, a gate opening formed between the first spacer and the second spacer, a first oxide region adjacent to and outside the first spacer, and a second oxide region adjacent to and outside the second spacer;
filling the gate opening with a compressive insulating material;
forming a first conductive via in the first oxide region, and a second conductive via in the second oxide region;
thereafter removing the first oxide region and the second oxide region;
and
depositing a tensile insulating material between the first conductive via and the first spacer, between the second conductive via and the second spacer, and over the compressive insulating material.

3 more elements

A method of fabricating a semiconductor device, the method comprising:

forming an NMOS device structure on a semiconductor substrate, the NMOS device structure comprising a first pair of spacers, compressive insulating material between the first pair of spacers, and oxide material adjacent to and outside the first pair of spacers;
forming a PMOS device structure on the semiconductor substrate, the PMOS device structure comprising a second pair of spacers, tensile insulating material between the second pair of spacers, and oxide material adjacent to and outside the second pair of spacers;
for the NMOS device structure:
forming first conductive vias in the oxide material of the NMOS device structure;
thereafter removing the oxide material of the NMOS device structure, resulting in first openings between the first pair of spacers and the first conductive vias;
and
depositing tensile insulating material in the first openings;
and
for the PMOS device structure:
forming second conductive vias in the oxide material of the PMOS device structure;
thereafter removing the oxide material of the PMOS device structure, resulting in second openings between the second pair of spacers and the second conductive vias;
and
depositing compressive insulating material in the second openings.

10 more elements

Dependencies are inferred from the claim text.

Gate straining in a semiconductor device

Life of this patent

Gate straining in a semiconductor device

Life of this patent

Abstract

Claims21