Use of low temperature anneal to provide low defect gate full silicidation

A method for manufacturing a semiconductor device, comprising:

• forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode;
• forming a metal layer over the gate electrode;
• and
• annealing the gate electrode in a presence of the metal layer to form a silicided gate electrode, wherein a maximum temperature of the annealing does not exceed about 340° C.

A method for manufacturing a semiconductor device, comprising:

• forming a substrate having a p-type metal oxide semiconductor (PMOS) device region and n-type metal oxide semiconductor (NMOS) device region;
• forming a first gate structure comprising a first gate dielectric and a first gate electrode over the substrate in the PMOS device region;
• forming a second gate structure comprising a second gate dielectric and a second gate electrode over the substrate in the NMOS device region;
• forming first source/drain regions in the substrate proximate the first gate structure;
• forming second source/drain regions in the substrate proximate the second gate structure;
• forming a metal layer in contact with the first gate electrode and the second gate electrode;
• and
• annealing the first gate electrode and the second gate electrode in a presence of the metal layer to form a first silicided gate electrode and a second silicided gate electrode, wherein a maximum temperature of the annealing does not exceed about 340° C.

A method for manufacturing a semiconductor device, comprising:

• selecting a maximum silicidation temperature based upon a desire to exclude a predetermined silicidation transient phase of a gate electrode material;
• forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode including the gate electrode material;
• forming a metal layer over the gate electrode;
• and
• annealing the gate electrode using the selected maximum silicidation temperature in a presence of the metal layer to form a silicided gate electrode.