Fabrication method of semiconductor integrated circuit device
OwnerYuji Wada, Akira Seito +1inventors
InventorsYuji Wada, Akira Seito, Masaaki Namba
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Abstract
A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.
Claims1
A fabrication method of semiconductor integrated circuit devices, comprising the steps of:
- mounting a plurality of semiconductor integrated circuit devices, obtained by encapsulating a plurality of semiconductor chips, including a logic circuit device or CPU and a memory circuit device, in one package, in a plurality of test boards;
- and
- conducting a memory test on each memory circuit device in the semiconductor integrated circuit devices while the test boards are placed in a thermostatic bath,
- wherein the thermostatic bath includes first and second slots which are different from each other in temperature.
Dependencies are inferred from the claim text.