High fidelity multiple resist patterning
AssigneeAdvanced Micro Devices, Inc.
InventorsThomas I. Wallow, Ryoung-Han Kim, Jongwook Kye
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AssigneeAdvanced Micro Devices, Inc.
InventorsThomas I. Wallow, Ryoung-Han Kim, Jongwook Kye
Estimating the term…
An integrated circuit fabrication process as described herein employs a double photoresist exposure technique. After creation of a first pattern of photoresist features on a wafer, a second photoresist layer is formed over the first pattern of photoresist features. The second photoresist layer is subjected to a reflow step that softens and relaxes the second photoresist material. This reflow step causes the exposed surface of the second photoresist layer to become substantially planar. Thereafter, the second photoresist layer can be exposed and developed to create a second pattern of photoresist features on the wafer. The planar surface of the second photoresist layer, which results from the reflow step, facilitates the creation of accurate, precise, and “high fidelity” photoresist features from the second photoresist material.
A method of creating photoresist features on a semiconductor wafer, the method comprising:
A method of processing a semiconductor wafer, the method comprising:
A method of processing a semiconductor wafer, the method comprising:
Dependencies are inferred from the claim text.