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US 2008/0291352 A1Published application
Digital circuit having correcting circuit and electronic apparatus thereof
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHajime Kimura
Life of this patent
Estimating the term…
Abstract
Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same to threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.
Claims11
A liquid crystal display device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- a capacitor;
- and
- a wiring,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the first transistor,
- wherein the first transistor and the third transistor are electrically connected in series between the wiring and a gate of the second transistor,
- wherein one terminal of the capacitor is electrically connected to a first terminal,
- wherein the gate of the second transistor is electrically connected to the other terminal of the capacitor, and
- wherein one of a source and a drain of the second transistor is electrically connected to a second terminal and the other one of the source and the drain of the second transistor is electrically connected to the wiring.
8 more elements
A liquid crystal display device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- a fourth transistor;
- a capacitor;
- a first wiring;
- and
- a second wiring,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the first transistor,
- wherein the first transistor and the third transistor are electrically connected in series between the first wiring and a gate of the second transistor,
- wherein one terminal of the capacitor is electrically connected to a first terminal,
- wherein the gate of the second transistor is electrically connected to the other terminal of the capacitor,
- wherein one of a source and a drain of the second transistor is electrically connected to a second terminal and the other one of the source and the drain of the second transistor is electrically connected to the first wiring, and
- wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the second transistor and the other one of the source and the drain of the fourth transistor is electrically connected to the second wiring.
11 more elements
A liquid crystal display device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- a fourth transistor;
- a capacitor;
- a first wiring;
- and
- a second wiring,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the first transistor,
- wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the fourth transistor,
- wherein the first transistor and the third transistor are electrically connected in series between the first wiring and a gate of the second transistor,
- wherein the gate of the first transistor is electrically connected to the other one of the source and the drain of the fourth transistor,
- wherein one terminal of the capacitor is electrically connected to a first terminal,
- wherein the gate of the second transistor is electrically connected to the other terminal of the capacitor, and
- wherein one of a source and a drain of the second transistor is electrically connected to a second terminal and the other one of the source and the drain of the second transistor is electrically connected to the first wiring.
12 more elements
A liquid crystal display device comprising:
- a first n-type transistor;
- a first p-type transistor;
- a second n-type transistor;
- a second p-type transistor;
- a third n-type transistor;
- a third p-type transistor;
- a first capacitor;
- a second capacitor;
- a first wiring;
- and
- a second wiring,
- wherein one of a source and a drain of the first n-type transistor is electrically connected to a gate of the first n-type transistor,
- wherein the first n-type transistor and the third n-type transistor are electrically connected in series between the first wiring and a gate of the second n-type transistor,
- wherein one terminal of the first capacitor is electrically connected to a first terminal,
- wherein the gate of the second n-type transistor is electrically connected to the other terminal of the first capacitor,
- wherein one of a source and a drain of the second n-type transistor is electrically connected to a second terminal and the other one of the source and the drain of the second n-type transistor is electrically connected to the first wiring,
- wherein one of a source and a drain of the first p-type transistor is electrically connected to a gate of the first p-type transistor,
- wherein the first p-type transistor and the third p-type transistor are electrically connected in series between the second wiring and a gate of the second p-type transistor,
- wherein one terminal of the second capacitor is electrically connected to the first terminal,
- wherein the gate of the second p-type transistor is electrically connected to the other terminal of the second capacitor, and
- wherein one of a source and a drain of the second p-type transistor is electrically connected to a second terminal and the other one of the source and the drain of the second p-type transistor is electrically connected to the second wiring.
18 more elements
A liquid crystal display device comprising:
- a first n-type transistor;
- a first p-type transistor;
- a second n-type transistor;
- a second p-type transistor;
- a third n-type transistor;
- a third p-type transistor;
- a fourth n-type transistor;
- a fourth p-type transistor;
- a first capacitor;
- a second capacitor;
- a first wiring;
- a second wiring;
- a third wiring;
- and
- a fourth wiring;
- wherein one of a source and a drain of the first n-type transistor is electrically connected to a gate of the first n-type transistor,
- wherein the first n-type transistor and the third n-type transistor are electrically connected in series between the first wiring and a gate of the second n-type transistor,
- wherein one terminal of the first capacitor is electrically connected to a first terminal,
- wherein the gate of the second n-type transistor is electrically connected to the other terminal of the first capacitor,
- wherein one of a source and a drain of the second n-type transistor is electrically connected to a second terminal and the other one of the source and the drain of the second n-type transistor is electrically connected to the first wiring,
- wherein one of a source and a drain of the fourth n-type transistor is electrically connected to the gate of the second n-type transistor and the other one of the source and the drain of the fourth n-type transistor is electrically connected to the second wiring,
- wherein one of a source and a drain of the first p-type transistor is electrically connected to a gate of the first p-type transistor,
- wherein the first p-type transistor and the third p-type transistor are electrically connected in series between the third wiring and a gate of the second p-type transistor,
- wherein one terminal of the second capacitor is electrically connected to the first terminal,
- wherein the gate of the second p-type transistor is electrically connected to the other terminal of the second capacitor,
- wherein one of a source and a drain of the second p-type transistor is electrically connected to a second terminal and the other one of the source and the drain of the second n-type transistor is electrically connected to the third wiring, and
- wherein one of a source and a drain of the fourth p-type transistor is electrically connected to the gate of the second p-type transistor and the other one of the source and the drain of the fourth p-type transistor is electrically connected to the fourth wiring.
24 more elements
Dependencies are inferred from the claim text.