Duty cycle correction circuit and method thereof
AssigneeNanya Technology Corporation
InventorWen-Chang Cheng
Life of this patent
Estimating the term…
Abstract
A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.
Claims15
A duty cycle correction circuit, comprising
- a frequency divider receiving a first clock signal and dividing frequency of the first clock signal to generate a second clock signal;
- a duty cycle detector receiving the second clock signal and a correction clock signal and generating a control signal according to the second clock signal and the correction clock signal ;
- and
- a delay circuit receiving the first clock signal and the control signal and adjusting a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.
A duty cycle correction method, comprising:
- dividing a frequency of a first clock signal to generate a second clock signal;
- charging a first terminal of a comparator by a first fixed current during a period of the first clock signal;
- charging a second terminal of the comparator by a second fixed current during the period of the first clock signal;
- comparing voltages of the first terminal and the second terminal of the comparator to generate a control signal;
- and
- adjusting a delay time of a falling edge of the first clock signal according to the control signal.
Dependencies are inferred from the claim text.