Clock generator for semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorHYUN WOO LEE
Life of this patent
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Abstract
The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second divider configured to divide a frequency of an output of the first delay unit; a second delay unit configured to delay the output of the second divider by second delay time; a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison; and a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator.
Claims10
A clock generator for a semiconductor memory apparatus, comprising:
- a first divider configured to divide a frequency of a first internal clock generated by using an external clock;
- a first delay unit configured to delay an output of the first divider by first delay time;
- a second divider configured to divide a frequency of an output of the first delay unit;
- a second delay unit configured to delay the output of the second divider by second delay time;
- a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison;
- and
- a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator.
Dependencies are inferred from the claim text.