Dll circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus

A DLL circuit of a semiconductor memory apparatus comprising:

• a frequency sensing unit configured to generate and output a high frequency signal or a low frequency signal on the basis of a control signal;
• a clock dividing unit configured to receive the high frequency signal, the low frequency signal and an internal clock thereby generating a divided clock, to output the internal clock as the divided clock when the low frequency signal is enabled, and to divide the internal clock when the high frequency clock is enabled;
• and
• a phase sensing unit configured to receive a high frequency signal, a low frequency signal, an internal clock and a feedback clock thereby outputting a first phase control signal and a second phase control signal,
• wherein the phase sensing unit is configured to compare the internal clock as a reference clock with the feedback clock as a comparing clock, thereby generating the first and second phase control signals when the high frequency signal is enabled;
• and to compare the feedback clock as the reference clock with the internal clock as the comparing clock thereby generating the first and second phase control signals having phases that are opposite to the phases of the first and second phase control signal when the high frequency signal is enabled.