System and method for fast re-locking of a phase locked loop circuit

A circuit for reducing a re-lock time of a phase locked loop (PLL) comprising:

• a capture control voltage module using parallel signals for capturing a control voltage when the PLL is in a lock mode;
• a force control voltage module operatively coupled to said capture control voltage module for instantaneously passing a voltage from a node corresponding to said control voltage when the PLL is turned on from a powered off state;
• a plurality of serial resistances operatively coupled to the capture control voltage module and the force control voltage module, the plurality of serial resistances connected between a reference voltage and a ground voltage;
• a loop filter module operatively coupled to said force control voltage module for stabilizing and storing the control voltage;
• and
• a timer module operatively coupled to the force control voltage module for turning off said force control voltage module after a pre-defined number of input cycles.

A method for reducing a relock time of a phase locked loop (PLL) comprising:

• providing signal patterns to a capture control voltage module through a pattern generator;
• capturing a control voltage using the capture control voltage module when the PLL is in a lock state;
• forcing the control voltage using a force control voltage module when the PLL is turned on from a powered down state;
• switching off the force control voltage module after receiving a time out signal from a timer;
• and
• resuming a phase locking by the PLL.

A method for reducing a relock time of a phase locked loop (PLL) comprising:

• capturing a control voltage using a capture control voltage module when the PLL is in a lock state;
• forcing the control voltage using a force control voltage module when the PLL is turned on from a powered down state;
• switching off the force control voltage module after receiving a time out signal from a timer;
• and
• resuming a phase locking by the PLL.

A circuit for use with a phase lock loop (PLL), comprising:

• a voltage control circuit adapted to receive a pattern of input voltages and a control voltage, and to output a stored control voltage;
• a force control voltage circuit coupled to the voltage control circuit to pass a stored control voltage to the voltage control circuit when the PLL is first powered up;
• and
• a plurality of series-coupled resistances coupled between a reference voltage and a ground voltage and further coupled to the voltage control circuit and to the force control voltage circuit to provide variable voltages thereto.

A system for reducing the relock time of a phase lock loop circuit, the system comprising:

• a capture control voltage circuit adapted to receive a pattern of input voltages, a control voltage, and to output a stored control voltage;
• a force control voltage module coupled to the voltage control circuit and adapted to receive the stored control voltage and to force the stored control voltage when the PLL is first powered up;
• a loop filter circuit coupled to the force control voltage circuit for stabilizing and storing the control voltage;
• and
• a timer circuit operatively coupled to the force control voltage circuit for turning off the force control voltage circuit after a predetermined number of input voltage cycles have been received.