Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsShinichi HASHIMOTO, Tadahiro Yoshida, Ryogo Yanagisawa
Life of this patent
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Abstract
A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
Claims42
1-4. (canceled)
A clock signal switching method comprising the steps of:
- generating, based on a switching signal used in selecting either a first clock signal or a second clock signal and based on the first clock signal, a first mask signal and a first synchronized switching signal each synchronous with the first clock signal, and also generating, based on the switching signal and the second clock signal, a second mask signal and a second synchronized switching signal each synchronous with the second clock signal;
- masking the first clock signal with the first mask signal to generate a first masked clock signal, and masking the second clock signal with the second mask signal to generate a second masked clock signal;
- selecting either the first synchronized switching signal or the second synchronized switching signal as a selected switching signal based on the switching signal;
- and
- selecting either the first masked clock signal or the second masked clock signal as a selected clock signal based on the selected switching signal.
8-11. (canceled)
A data bus switching method comprising the steps of:
- generating a first mask signal and a first synchronized switching signal, which are each synchronous with the first clock signal, based on a switching signal used in selecting either a first clock signal inputted via a first data bus or a second clock signal inputted via a second data bus and based on the first clock signal, and also generating a second mask signal and a second synchronized switching signal, which are each synchronous with the second clock signal, based on the switching signal and the second clock signal;
- masking the first clock signal with the first mask signal, thereby generating a first masked clock signal;
- masking the second clock signal with the second mask signal, thereby generating a second masked clock signal;
- selecting either the first synchronized switching signal or the second synchronized switching signal as a selected switching signal based on the switching signal;
- selecting either the first masked clock signal or the second masked clock signal as a selected clock signal based on the selected switching signal;
- and
- selecting either a first data signal or a second data signal as a selected data signal based on the selected switching signal, the first data signal being inputted via the first data bus and synchronous with the first clock signal, the second data signal being inputted via the second data bus and synchronous with the second clock signal.
A clock signal switching device comprising:
- first clock signal mask means for masking a first clock signal with a first mask signal, thereby generating a first masked clock signal;
- second clock signal mask means for masking a second clock signal with a second mask signal, thereby generating a second masked clock signal;
- and
- masked clock signal selection means for selecting either the first masked clock signal or the second masked clock signal as a selected clock signal based on a switching signal used in selecting either the first clock signal or the second clock signal.
A data bus switching device comprising:
- first clock signal mask means for masking a first clock signal inputted via a first data bus with a first mask signal, thereby generating a first masked clock signal;
- second clock signal mask means for masking a second clock signal inputted via a second data bus with a second mask signal, thereby generating a second masked clock signal;
- masked clock signal selection means for selecting either the first masked clock signal or the second masked clock signal as a selected clock signal based on a switching signal used in selecting either the first clock signal or the second clock signal;
- and
- data signal selection means for selecting either a first data signal or a second data signal as a selected data signal based on the switching signal, the first data signal being inputted via the first data bus and synchronous with the first clock signal, the second data signal being inputted via the second data bus and synchronous with the second clock signal.
A clock signal switching device comprising:
- first signal synchronization generation means for generating, based on a switching signal used in selecting either a first clock signal or a second clock signal and based on the first clock signal, a first mask signal and a first synchronized switching signal each synchronous with the first clock signal;
- second signal synchronization generation means for generating, based on the switching signal and the second clock signal, a second mask signal and a second synchronized switching signal each synchronous with the second clock signal;
- synchronized switching signal selection means for selecting either the first synchronized switching signal or the second synchronized switching signal as a selected switching signal based on the switching signal;
- clock signal selection means for selecting either the first clock signal or the second clock signal as a selected clock signal based on the selected switching signal;
- synthesized mask signal generation means for generating a synthesized mask signal having a masking portion where a masking portion of the first mask signal and a masking portion of the second mask signal overlap each other;
- and
- clock signal mask means for masking the selected clock signal with the synthesized mask signal.
A clock signal switching method comprising the steps of:
- generating, based on a switching signal used in selecting either a first clock signal or a second clock signal and based on the first clock signal, a first mask signal and a first synchronized switching signal each synchronous with the first clock signal, and also generating, based on the switching signal and the second clock signal, a second mask signal and a second synchronized switching signal each synchronous with the second clock signal;
- selecting either the first synchronized switching signal or the second synchronized switching signal as a selected switching signal based on the switching signal;
- selecting either the first clock signal or the second clock signal as a selected clock signal based on the selected switching signal;
- generating a synthesized mask signal having a masking portion where a masking portion of the first mask signal and a masking portion of the second mask signal overlap each other;
- and
- masking the selected clock signal with the synthesized mask signal.
A data bus switching device comprising:
- first signal synchronization generation means for generating a first mask signal and a first synchronized switching signal based on a switching signal used in selecting either a first clock signal inputted via a first data bus or a second clock signal inputted via a second data bus and based on the first clock signal, the first mask signal and the first synchronized switching signal each being synchronous with the first clock signal;
- second signal synchronization generation means for generating, based on the switching signal and the second clock signal, a second mask signal and a second synchronized switching signal each synchronous with the second clock signal;
- synchronized switching signal selection means for selecting either the first synchronized switching signal or the second synchronized switching signal as a selected switching signal based on the switching signal;
- clock signal selection means for selecting either the first clock signal or the second clock signal as a selected clock signal based on the selected switching signal;
- synthesized mask signal generation means for generating a synthesized mask signal having a masking portion where a masking portion of the first mask signal and a masking portion of the second mask signal overlap each other;
- clock signal mask means for masking the selected clock signal with the synthesized mask signal;
- and
- data signal selection means for selecting either a first data signal or a second data signal as a selected data signal based on the selected switching signal, the first data signal being inputted via the first data bus and synchronous with the first clock signal, the second data signal being inputted via the second data bus and synchronous with the second clock signal.
A data bus switching method comprising the steps of:
- generating a first mask signal and a first synchronized switching signal, which are each synchronous with the first clock signal, based on a switching signal used in selecting either a first clock signal inputted via a first data bus or a second clock signal inputted via a second data bus and based on the first clock signal, and also generating a second mask signal and a second synchronized switching signal, which are each synchronous with the second clock signal, based on the switching signal and the second clock signal;
- selecting either the first synchronized switching signal or the second synchronized switching signal as a selected switching signal based on the switching signal;
- selecting either the first clock signal or the second clock signal as a selected clock signal based on the selected switching signal;
- generating a synthesized mask signal having a masking portion where a masking portion of the first mask signal and a masking portion of the second mask signal overlap each other;
- masking the selected clock signal with the synthesized mask signal;
- and
- selecting either a first data signal or a second data signal as a selected data signal based on the selected switching signal, the first data signal being inputted via the first data bus and synchronous with the first clock signal, the second data signal being inputted via the second data bus and synchronous with the second clock signal.
A clock signal switching device comprising:
- clock signal selection means for selecting either a first clock signal or a second clock signal as a selected clock signal based on a switching signal used in selecting either the first clock signal inputted via a first data bus or the second clock signal inputted via a second data bus, and
- clock signal mask means for masking the selected clock signal with an inputted mask signal.
A data bus switching device comprising:
- clock signal selection means for selecting either a first clock signal or a second clock signal as a selected clock signal based on a switching signal used in selecting either the first clock signal inputted via a first data bus or the second clock signal inputted via a second data bus,
- clock signal mask means for masking the selected clock signal with an inputted mask signal, and
- data signal selection means for selecting either a first data signal or a second data signal as a selected data signal based on the switching signal, the first data signal being inputted via the first data bus and synchronous with the first clock signal, the second data signal being inputted via the second data bus and synchronous with the second clock signal.
Dependencies are inferred from the claim text.