Level converter
AssigneeFujitsu Limited
InventorTomohiko KOTO
Life of this patent
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Abstract
A level converter comprising an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal; and a shift circuit that outputs an output signal generated by shifting a voltage level of the input signal, the shift circuit including: a latch circuit having: a first inverter circuit provided in a first path between a second high power source and the low power source; and a second inverter circuit provided in a second path between the second high power source and the low power source, wherein the latch circuit is formed by coupling an input terminal and an output terminal of the first inverter circuit and the second inverter circuit; a first transistor coupled to the first path; and a second transistor coupled to the second path.
Claims20
A level converter comprising:
- an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal in accordance with an input signal;
- and
- a shift circuit that outputs an output signal generated by shifting a voltage level of the input signal, the shift circuit including:
- a latch circuit having:
- a first inverter circuit provided in a first path between a second high power source and the low power source,
- wherein the second high power source is different from the first high power source;
- and
- a second inverter circuit provided in a second path between the second high power source and the low power source,
- wherein the latch circuit is formed by coupling an input terminal and an output terminal of the first inverter circuit and the second inverter circuit, and wherein the latch circuit latches the first signal and the second signal;
- a first transistor coupled to the first path;
- a second transistor coupled to the second path;
- and
- a control signal line that controls a gate potential of one of the first transistor and the second transistor.
A level converter comprising:
- an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal in accordance with an input signal;
- and
- a shift circuit that outputs an output signal generated by shifting a voltage level of the input signal, the shift circuit including:
- a latch circuit having:
- a first inverter circuit provided in a first path between a second high power source and the low power source, wherein the second high power source is different from the first high power source;
- and
- a second inverter circuit provided in a second path between the second high power source and the lower power source,
- wherein an input terminal and an output terminal of the first inverter circuit and the second inverter circuit are coupled, and wherein the latch circuit latches the first signal and the second signal;
- a first transistor coupled to the first path;
- and
- a second transistor coupled to the second path,
- wherein, when a potential of the second high power source is lower than or equal to a predetermined level, a gate potential of one of the first transistor and the second transistor is controlled to a middle level potential between the potential of the second high power source and the low power source, and
- wherein, when the potential of the second high power source is higher than the predetermined level, the gate potential is controlled so that one of the first transistor and the second transistor is turned ON.
A level converter comprising:
- an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal in accordance with an input signal;
- and
- a shift circuit that outputs an output signal generated by shifting a voltage level of the input signal, the shift circuit including:
- a latch circuit having:
- a first inverter circuit provided in a first path between a second high power source and the low power source, wherein the second high power source is different from of the first high power source;
- and
- a second inverter circuit provided in a second path between the second high power source and the low power source,
- wherein an input terminal and an output terminal of the first inverter circuit and the second inverter circuit are coupled, wherein the latch circuit latches the first signal and the second signal;
- a first element coupled to the second high power source and the first inverter circuit;
- and
- a second element coupled to the low power source and the second inverter circuit,
- wherein, at least when a potential of the second high power source is lower than or equal to a predetermined level, one of the first element and the second element flows current.
Dependencies are inferred from the claim text.