Probe needle protection method for high current probe testing of power devices

A method for applying high current test stimuli to a semiconductor device in wafer or chip form, said semiconductor device including a plurality of contact points, comprising:

• coupling a plurality of probes to at least one of the plurality of contact points on the semiconductor device;
• independently limiting current flow through each probe of the plurality of probes to a predetermined level;
• and
• providing a signal when detected current in any probe exceeds a predetermined level.

A test apparatus for applying high current test stimuli to a semiconductor device in wafer or chip form, said semiconductor device including a plurality of contact points, comprising:

• a plurality of probes for electrically coupling to at least one of the plurality of contact points on the semiconductor device
• a plurality of current limiters electrically coupled to respective ones of the plurality of probes, said current limiters operative to limit current flow in a corresponding probe;
• a voltage protection circuit electrically coupled to said plurality of current limiters, said voltage protection circuit operative to protect the plurality of probes from an over-voltage condition;
• and
• a trigger circuit electrically coupled to each of the plurality of current limiters and to the protection circuit, said trigger circuit operative to detect a voltage drop across the current limiters, and when the voltage drop across any current limiter exceeds a predetermined level, the trigger circuit is operative to command the voltage protection circuit to enter a protection mode.