Power supply circuit and semiconductor memory

A power supply circuit that outputs a set voltage from an output terminal, comprising:

• a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal;
• a voltage detecting circuit that outputs a first detecting signal when the voltage outputted from the boosting circuit is not lower than a first detection voltage set lower than the set voltage, and outputs a second detecting signal when the voltage outputted from the boosting circuit is not lower than the set voltage;
• and
• a clock signal generating circuit that outputs, based on a reference clock signal, a clock signal and an inverted clock signal obtained by inverting the clock signal, and stops outputs of the clock signal and the inverted clock signal in response to the second detecting signal,
• the boosting circuit comprising:
• a first MOS transistor of a first conductivity type having one end connected to the power supply and a gate fed with the clock signal;
• a first capacitor having one end connected to an other end of the first MOS transistor;
• a first logic circuit fed with the inverted clock signal and a limit signal generated based on the first detecting signal to limit a boosting capability, outputting the inverted clock signal to an other end of the first capacitor, and limiting the output of the inverted clock signal in response to the limit signal;
• a second MOS transistor of a second conductivity type having one end connected to the one end of the first capacitor and a gate fed with the clock signal;
• a third MOS transistor of the first conductivity type having one end connected to an other end of the second MOS transistor, an other end connected to ground, and a gate connected to the gate of the second MOS transistor;
• a fourth MOS transistor of the first conductivity type having one end connected to the power supply and a gate fed with the inverted clock signal;
• a second capacitor having one end connected to an other end of the fourth MOS transistor;
• a second logic circuit fed with the limit signal and the clock signal, outputting the clock signal to an other end of the second capacitor, and limiting the output of the clock signal in response to the limit signal;
• a fifth MOS transistor of the second conductivity type having one end connected to the one end of the second capacitor and a gate fed with the inverted clock signal;
• a sixth MOS transistor of the first conductivity type having one end connected to an other end of the fifth MOS transistor, an other end connected to the ground, and a gate connected to the gate of the fifth MOS transistor;
• a seventh MOS transistor of the first conductivity type having one end connected to the power supply and a gate fed with the clock signal;
• a third capacitor having one end connected to the other end of the seventh MOS transistor and an other end fed with the inverted clock signal;
• a first diode having an anode connected to the other end of the seventh MOS transistor;
• a second diode having an anode connected to a cathode of the first diode and a cathode connected to the output terminal;
• an eighth MOS transistor of the first conductivity type having one end connected to the power supply and a gate fed with the inverted clock signal;
• a fourth capacitor having one end connected to the other end of the eighth MOS transistor and an other end fed with the clock signal;
• a third diode having an anode connected to the other end of the eighth MOS transistor;
• a fourth diode having an anode connected to a cathode of the third diode and a cathode connected to the output terminal;
• a fifth capacitor having one end connected to the other end of the second MOS transistor and an other end connected to the cathode of the third diode;
• and
• a sixth capacitor having one end connected to the other end of the fifth MOS transistor and an other end connected to the cathode of the first diode.

A semiconductor memory comprising a power supply circuit that outputs a set voltage from an output terminal,

• the power supply circuit comprising:
• a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal;
• a voltage detecting circuit that outputs a first detecting signal when the voltage outputted from the boosting circuit is not lower than a first detection voltage set lower than the set voltage, and outputs a second detecting signal when the voltage outputted from the boosting circuit is not lower than the set voltage;
• and
• a clock signal generating circuit that outputs, based on a reference clock signal, a clock signal and an inverted clock signal obtained by inverting the clock signal, and stops outputs of the clock signal and the inverted clock signal in response to the second detecting signal,
• the boosting circuit comprising:
• a first MOS transistor of a first conductivity type having one end connected to the power supply and a gate fed with the clock signal;
• a first capacitor having one end connected to an other end of the first MOS transistor;
• a first logic circuit fed with the inverted clock signal and a limit signal generated based on the first detecting signal to limit a boosting capability, outputting the inverted clock signal to an other end of the first capacitor, and limiting the output of the inverted clock signal in response to the limit signal;
• a second MOS transistor of a second conductivity type having one end connected to the one end of the first capacitor and a gate fed with the clock signal;
• a third MOS transistor of the first conductivity type having one end connected to an other end of the second MOS transistor, an other end connected to ground, and a gate connected to the gate of the second MOS transistor;
• a fourth MOS transistor of the first conductivity type having one end connected to the power supply and a gate fed with the inverted clock signal;
• a second capacitor having one end connected to an other end of the fourth MOS transistor;
• a second logic circuit fed with the limit signal and the clock signal, outputting the clock signal to an other end of the second capacitor, and limiting the output of the clock signal in response to the limit signal;
• a fifth MOS transistor of the second conductivity type having one end connected to the one end of the second capacitor and a gate fed with the inverted clock signal;
• a sixth MOS transistor of the first conductivity type having one end connected to an other end of the fifth MOS transistor, an other end connected to the ground, and a gate connected to the gate of the fifth MOS transistor;
• a first diode having an anode connected to the one end of the second MOS transistor;
• a second diode having an anode connected to a cathode of the first diode and a cathode connected to the output terminal;
• a third diode having an anode connected to the one end of the fifth MOS transistor;
• a fourth diode having an anode connected to a cathode of the third diode and a cathode connected to the output terminal;
• a third capacitor having one end connected to the other end of the second MOS transistor and an other end connected to the cathode of the third diode;
• and
• a fourth capacitor having one end connected to the other end of the fifth MOS transistor and an other end connected to the cathode of the first diode.