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US 2008/0290495 A1Published application
Low noise semiconductor device
AssigneesHitachi, Ltd., Elpida Memory, Inc.
InventorsYutaka Uematsu, Tatsuya Saito, Hideki Osaka, Yoji Nishio, Shunichi Saito
Life of this patent
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Abstract
As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
Claims14
A semiconductor device comprising:
- a semiconductor chip having at least a power terminal and a ground terminal, and
- a semiconductor package having a first terminal and a second terminal for electrical connection to the power terminal and the ground terminal, respectively, a third terminal and a fourth terminal for external connection, a first power feed route for connection between the first terminal and the third terminal, and a second power feed route for connection between the second terminal and the fourth terminal,
- wherein the first power feed route is formed of a first conductor having a first resistivity and a second conductor having a second resistivity higher than the first resistivity.
A semiconductor device comprising:
- a semiconductor chip having at least a power terminal and a ground terminal, and
- a semiconductor package having a first terminal for electrical connection to the power terminal, a second terminal for electrical connection to the ground terminal, a third terminal, a fourth terminal, fifth terminal and a sixth terminal for external connection, further provided with first wiring for linking the first terminal with third terminal, second wiring for linking the first terminal with fourth terminal, third wiring for linking the second terminal with fifth terminal, and fourth wiring for linking the second terminal with sixth terminal, the first wiring and third wiring being formed of a first conductor having a first resistivity and the second wiring and fourth wiring being formed of a second conductor having a second resistivity higher than the first resistivity,
- wherein a power feed circuit is formed which establishes connection from one decoupling capacitor to the third terminal and fourth terminal via separate routes and returns to the decoupling capacitor via a return route from the fifth terminal and sixth terminal.
A semiconductor device comprising:
- a semiconductor package mounted with a semiconductor chip and having a power terminal and a ground terminal connected from outside to feed power to the semiconductor chip,
- a printed circuit board mounted with the semiconductor package and having as inner layers thereof a power supply layer electrically connected to the power terminal and a ground layer electrically connected to the ground terminal, and
- a decoupling capacitor connected to a first interconnecting electrode and a second interconnecting electrode, constituting a pair on a surface of the printed circuit board and fitted to the printed circuit board,
- wherein the semiconductor device having first wiring which, as part of a power feed circuit which reaches the semiconductor chip from the decoupling capacitor and returns again, links a first VIA electrode connected to the power supply layer with the first interconnecting electrode and second wiring which links a second VIA electrode connected to the ground layer with the second interconnecting electrode, and the first wiring and the second wiring being respectively formed of a first conductor having a first resistivity and a second conductor having a second resistivity higher than the first resistivity.
1 more element
A semiconductor device comprising:
- a semiconductor package mounted with a semiconductor chip and having a power terminal and a ground terminal connected from outside to feed power to the semiconductor chip,
- a printed circuit board mounted with the semiconductor package and provided at least with a power supply layer electrically connected to the power terminal and a ground layer electrically connected to the ground terminal, and
- a decoupling capacitor connected to a first interconnecting electrode and a second interconnecting electrode, constituting a pair on a surface of the printed circuit board and fitted to the printed circuit board,
- wherein the first interconnecting electrode and second interconnecting electrode respectively have a low resistance area of a first resistivity and a high resistance area of a second resistivity higher than the first resistivity, and the printed circuit board is provided with a current route which leads from the low resistance area of the first interconnecting electrode to the power supply layer via first wiring on the surface of the printed circuit board, another current route which leads to the power supply layer via a first pad-on VIA which directly links to the high resistance area of the first interconnecting electrode, and still another current route which leads to the ground layer from the low resistance area of the second interconnecting electrode via second wiring on the surface of the printed circuit board, and yet another current route which leads to the ground layer via a second pad-on VIA which directly links to the high resistance area of the second interconnecting electrode.
1 more element
Dependencies are inferred from the claim text.