Thin silicon-on-insulator double-diffused metal oxide semiconductor transistor
AssigneeSharp Laboratories of America, Inc.
InventorsSheng Teng Hsu, Jong-Jan Lee
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AssigneeSharp Laboratories of America, Inc.
InventorsSheng Teng Hsu, Jong-Jan Lee
Estimating the term…
A method is provided for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness. The method provides a SOI substrate with a Si top layer having a surface. A thinned area of the Si top layer is formed, and a source region is formed in the thinned Si top layer area. The drain region is formed in an un-thinned area of the Si top layer. The channel has a first thickness adjacent the source region with first-type dopant, and a second thickness, greater than the first thickness, adjacent the drain region. The channel also has a sloped thickness between the first and second thicknesses. The second and sloped thicknesses have a second-type dopant, opposite of the first-type dopant. A stepped gate overlies the channel.
A method for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness, the method comprising:
The method of claim 8 wherein thermally diffusing B ions from the source into the channel first thickness includes:
The method of claim 10 wherein forming the source and drain regions includes:
A silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness, the DMOST comprising:
The DMOST of claim 12 wherein the source region first thickness is in a range of 10 to 100 nanometers (nm).
The DMOST of claim 17 wherein the channel first thickness area is p doped to a density in a range of 1×1016 to 1×1018 per cubic cm−3.
The DMOST of claim 18 wherein the source region is n+ doped to density in a range of 1×1019 to 1×1021 cm−3;
Dependencies are inferred from the claim text.