Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
AssigneeCypress Semiconductor Corporation
InventorsSagy Levy, Fredrick B. Jenne, Krishnaswamy Ramkumar
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Abstract
A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.
Claims20
A nonvolatile charge trap memory device, comprising:
- a substrate having a channel region, a source region and a drain region;
- and
- a gate stack disposed above the substrate over the channel region and between the source region and the drain region, wherein the gate stack comprises a multi-layer charge-trapping region having at least a deuterated layer.
A nonvolatile charge trap memory device, comprising:
- a substrate having a channel region, a source region and a drain region;
- and
- a gate stack disposed above the substrate over the channel region and between the source region and the drain region, wherein the gate stack comprises:
- a tunnel dielectric layer disposed above the channel region;
- a multi-layer charge-trapping region disposed above the tunnel dielectric layer, wherein the multi-layer charge-trapping region comprises a first deuterated layer above the tunnel dielectric layer, a charge-trapping layer disposed above the first deuterated layer, and a second deuterated layer disposed above the charge-trapping layer;
- a top dielectric layer disposed above the second deuterated layer of the multi-layer charge-trapping region;
- and
- a gate layer disposed above the top dielectric layer.
A method of fabricating a nonvolatile charge trap memory device, comprising:
- providing a substrate;
- forming a gate stack above the substrate, wherein forming the gate stack comprises:
- forming a tunnel dielectric layer above the substrate;
- forming a multi-layer charge-trapping region above the tunnel dielectric layer, wherein the multi-layer charge-trapping region comprises a deuterated layer;
- forming a top dielectric layer above the multi-layer charge-trapping region;
- forming a gate layer above the top dielectric layer;
- and
- patterning the tunnel dielectric layer, the multi-layer charge-trapping region, the top dielectric layer, and the gate layer;
- and
- forming a source region and a drain region in the substrate and on other side of the gate stack to provide a channel region in the substrate and below the gate stack.
Dependencies are inferred from the claim text.