Nonvolatile charge trap memory device having <100> crystal plane channel orientation

A nonvolatile charge trap memory device, comprising:

• an isolation structure formed in a substrate;
• an active region formed in the substrate and adjacent to the isolation structure;
• a channel region formed in the active region, wherein the channel region has a channel length with <100> crystal plane orientation;
• a source region and a drain region formed in the active region, wherein the channel region is between the source region and the drain region;
• and
• a gate stack disposed above the channel region.

A nonvolatile charge trap memory device, comprising:

• a channel region formed in an active region, wherein the channel region has a top surface having <100> crystal plane orientation and a sidewall surface having <100> crystal plane orientation;
• an isolation structure adjacent to the sidewall of the channel region, wherein the top surface of the channel region is above a top surface of the isolation structure;
• and
• a gate stack disposed over the top surface and the sidewall surface of the channel region.

A method of fabricating a nonvolatile charge trap memory device, comprising:

• forming an isolation region and an active region in a substrate, wherein the active region is adjacent to the isolation region;
• forming a gate stack above the active region;
• and
• forming a source region and a drain region in the active region and on other side of the gate stack to provide a channel region in the active region, wherein the channel region has a channel length with <100> crystal plane orientation between the source region and the drain region.