Memory cell and method for manufacturing and operating the same

A method for manufacturing a memory cell comprising the steps of:

• providing a substrate having a liner layer and a material layer sequentially formed thereon;
• forming a patterned mask layer on the substrate;
• trimming the patterned mask layer;
• removing a portion of the material layer, a portion of the liner layer and a portion of the substrate to define a plurality of fin structures in the substrate by using the patterned mask layer as a mask;
• removing the patterned mask layer;
• forming a plurality of isolation structures among the fin structures and the surface of the isolation structures is lower than the surface of the fin structures;
• forming a charge trapping structure on the substrate, covering the fin structures;
• removing a portion of the charge trapping structure to expose the material layer;
• performing a treatment process to turn the material layer into a protection layer;
• forming a gate on the substrate and over the protection layer, the charge trapping structure, and the fin structure;
• and
• forming a source/drain region in the fin structure exposed by both sides of the gate.

A method for operating a memory cell that is disposed on a substrate having a plurality of isolation structures that define at least one fin structure having a surface that is higher than the surface of the isolation structures, wherein the memory cell comprises a gate disposed on the substrate and straddled the fin structure, a first doped region and a second doped region that are respectively disposed in the fin structure formed on the two sides of the gate, a first charge trapping structure and a second charge trapping structures disposed between the gate and the fin structure that are respectively formed on both sidewalls of the fin structure;

• wherein the first charge trapping structure comprises a first storage region that is adjacent to the first doped region and a second storage region that is adjacent to the second doped region and the second charge trapping structure comprises a third storage region that is adjacent to the first doped region and a fourth storage region that is adjacent to the second doped region;
• and a protection layer that is disposed between the upper portion of the fin structure and the gate, separating the first charge trapping structure and the second charge trapping structure, the method comprising:
• performing a programming operation by applying a first voltage to the gate, a second voltage to the first doped region, and a third voltage to the second doped region, wherein the first voltage is greater than the third voltage and the third voltage is greater than the second voltage, to inject charges to the second storage region and the fourth storage region that are adjacent to the second doped region.