Semiconductor device having reduced sub-threshold leakage
AssigneeMicron Technology, Inc.
InventorsDavid K. Hwang, Larson Lindholm
Life of this patent
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Abstract
A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.
Claims24
A semiconductor device comprising:
- a semiconductor substrate;
- opposed source and drain pillars fabricated in the semiconductor substrate;
- a fin fabricated in the semiconductor substrate and interposed between the source and drain pillars;
- and
- a cavity formed in the semiconductor substrate, the cavity extending at least partially between the fin and the semiconductor substrate.
A semiconductor device comprising:
- a semiconductor substrate;
- opposed source and drain pillars fabricated in the semiconductor substrate;
- a fin fabricated in the semiconductor substrate and interposed between the source and drain pillars;
- and
- a cavity formed in the semiconductor substrate extending at least partially beneath at least one of the source pillar and the drain pillar.
A semiconductor device for use as an access transistor in a dynamic random access memory, the semiconductor device comprising:
- a semiconductor substrate;
- a first pillars fabricated in the semiconductor substrate and coupled to a digit line;
- a second pillar fabricated in the semiconductor substrate and coupled to a first memory cell capacitor;
- a first fin fabricated in the semiconductor substrate and interposed between the first pillar and the second pillar;
- a first cavity formed in the semiconductor substrate, the first cavity extending at least partially between the first fin and the semiconductor substrate;
- a third pillar fabricated in the semiconductor substrate and coupled to a second memory cell capacitor;
- a second fin fabricated in the semiconductor substrate and interposed between the first pillar and the third pillar;
- and
- a second cavity formed in the semiconductor substrate, the second cavity extending at least partially between the second fin and the semiconductor substrate.
A semiconductor device for use as an access transistor in a dynamic random access memory, the semiconductor device comprising:
- a semiconductor substrate;
- a first pillars fabricated in the semiconductor substrate and coupled to a digit line;
- a second pillar fabricated in the semiconductor substrate and coupled to a first memory cell capacitor;
- a first fin fabricated in the semiconductor substrate and interposed between the first pillar and the second pillar;
- a first cavity formed in the semiconductor substrate, the first cavity extending at least partially beneath the second pillar;
- between the first fin and the semiconductor substrate;
- a third pillar fabricated in the semiconductor substrate and coupled to a second memory cell capacitor;
- a second fin fabricated in the semiconductor substrate and interposed between the first pillar and the third pillar;
- and
- a second cavity formed in the semiconductor substrate, the second cavity extending at least partially beneath the third pillar.
A method of fabricating a pair of access devices for a dynamic random access memory device, the method comprising:
- fabricating a pair of FinFET devices on a semiconductor substrate, the FinFet devices having a common digit line pillar, respective memory cells pillars and respective fins extending between the command digit line pillar and respective ones of the memory cell pillars;
- anisotropically etching the semiconductor substrate to form a shallow trench isolation structures adjacent at least the fins;
- and
- isotropically etching the semiconductor substrate within the shallow trench isolation structures to form respective cavities in the semiconductor structure extending from respective ones of the shallow trench isolation structures at least partially beneath at least the respective fins.
A method of fabricating a semiconductor device on a semiconductor substrate, the method comprising:
- fabricating a FinFET device in the semiconductor substrate having first and second pillars and a fin extending therebetween;
- anisotropically etching the semiconductor substrate to form a shallow trench isolation structure adjacent at least one of the first pillar, the second pillar and the fin;
- and
- isotropically etching the semiconductor substrate within at least a portion of the shallow trench isolation structure to form a cavity in the semiconductor structure extending from the shallow trench isolation structure beneath at least one of the first pillar, the second pillar and the fin.
Dependencies are inferred from the claim text.