Capacitance noise shielding plane for imager sensor devices

A backside illumination imager sensor pixel comprising:

• a photodiode region on a first substrate;
• metal interconnect lines on a second substrate;
• and
• a conductive material electrically isolating the photodiode region on the first substrate from the metal interconnect lines on the second substrate.

An imager sensor pixel array comprising:

• individual imager sensor pixels comprising:
• a photodiode region;
• metal interconnect lines;
• and
• an optically clear conductive material electrically isolating the photodiode region from the metal interconnect lines.

A processor system comprising:

• a processor;
• an imager device having an imager sensor pixel array with individual imager sensor pixels comprising:
• a photodiode region;
• metal interconnect lines;
• and
• a conductive material electrically isolating the photodiode region from the metal interconnect lines, such that parasitic capacitance is common to all imager sensor pixels of the imager sensor array, each parasitic capacitance is between the optically clear conductive material and underlying conductive regions of each imager sensor pixel.