Transistor package with wafer level dielectric isolation

Abstract

A low cost transistor package is provided for high power applications. The package provides high thermal conductivity and dissipation for a silicon transistor die, high current carrying capability and isolation, and high power and thermal cycle life performance and reliability. A dielectric layer is fixed to a silicon transistor die, for coupling to a heat conducting buffer and attachment to a substrate. The dielectric layer is fixed to the die by growing the dielectric layer, depositing the dielectric layer, or applying the dielectric layer using a plasma spray. In an aspect, a conductive layer is formed to the silicon transistor die by a thermal or kinetic spray process, and the dielectric layer is applied to the conductive layer. The dielectric layer may also be established either before or after the transistor fabrication. Electrical and thermal interconnects are advantageously positioned from opposite sides of the silicon transistor die.

Dependencies are inferred from the claim text.