Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device

A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain, wherein the semiconductor further comprising:

• a source metal connected to said source region, and a gate metal configured as a metal stripe surrounding a peripheral region of said substrate connected to a gate pad wherein said gate metal and said gate pad are separated from said source metal by a metal gap;
• and
• an ESD protection circuit comprising at least two ESD protection stage with each stage includes a plurality of doped dielectric regions of opposite conductivity types constituting ESD diodes extending across said metal gap and connected between said gate metal and said source metal on said peripheral region of said substrate wherein each of said ESD protection stage have different widths and different number of pairs of doped dielectric regions.

A semiconductor power device supported on a semiconductor substrate comprising:

• an ESD protection circuit comprising at least two ESD protection stage with each stage includes a plurality of doped dielectric regions of opposite conductivity types constituting ESD diodes extending between a gate metal and a source metal on a peripheral region of said substrate wherein a first ESD protection stage have a width based on an predefined ESD rating and a largest number of pairs of doped dielectric regions among said multiple ESD protection stages and based on a predefined gate leakage current.

A method for protecting a semiconductor power device supported on a semiconductor substrate from an ESD pulse comprising:

• forming an ESD protection circuit with at least two ESD protection stages by including in each stage a plurality of doped dielectric regions of opposite conductivity types for functioning as ESD diodes extending between a gate metal and a source metal on a peripheral region of said substrate wherein a first ESD protection stage;
• and
• forming a first ESD protection stage with a width based on an predefined ESD rating and a largest number of pairs of doped dielectric regions among said multiple ESD protection stages based on a predefined gate leakage current.