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US 2008/0290345 A1Published application
Semiconductor device having display device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHisashi Ohtani
Life of this patent
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Abstract
A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).
Claims9
A display device comprising:
- a substrate having an insulating surface;
- a first insulating film comprising silicon oxide formed on the substrate;
- a semiconductor layer formed on the substrate, said semiconductor layer including at least a channel region;
- a second insulating film comprising silicon oxide formed over the semiconductor layer;
- a third insulating film comprising silicon nitride formed over the second insulating film;
- a gate electrode formed over the channel region of the semiconductor layer with the second insulating film and the third insulating film interposed therebetween;
- a fourth insulating film comprising silicon nitride formed over the semiconductor layer, the first and second and third insulating films and the gate electrode;
- and
- a pixel electrode formed over said fourth insulating film wherein said pixel electrode is electrically connected to the semiconductor layer,
- wherein said fourth insulating film is in direct contact with an upper surface of the third insulating film and an upper surface of the gate electrode and side surfaces of the gate electrode.
7 more elements
A display device comprising:
- a substrate having an insulating surface;
- a first insulating film comprising silicon oxide formed on the substrate;
- a semiconductor layer formed on the substrate, said semiconductor layer including at least a channel region;
- a second insulating film comprising silicon oxide formed over the semiconductor layer;
- a third insulating film comprising silicon nitride formed over the second insulating film;
- a gate electrode formed over the channel region of the semiconductor layer with the second insulating film and the third insulating film interposed therebetween;
- a fourth insulating film comprising silicon nitride formed over the semiconductor layer, the first and second and third insulating films and the gate electrode;
- a electrode formed over the fourth insulating film wherein said electrode is electrically connected to the semiconductor layer;
- a fifth insulating film formed over the electrode;
- and
- an indium tin oxide film formed over said fifth insulating film wherein said indium tin oxide film is electrically connected to the electrode,
- wherein said fourth insulating film is in direct contact with an upper surface of the third insulating film and an upper surface of the gate electrode and side surfaces of the gate electrode.
9 more elements
Dependencies are inferred from the claim text.