Circuit design verification method and apparatus and computer readable medium

A circuit design verification apparatus comprising:

• an input accepting unit configured to accept input of a circuit description which describes a circuit by using a plurality of conditional statements each including one or more conditional elements;
• an extracting unit configured to extract each conditional statement included in the circuit description and each conditional element included in the conditional statements;
• an executing unit configured to execute the circuit description by using test data for the circuit and;
• a table generating unit configured to generate a table including verification information for each conditional statement, the verification information representing (A1) whether each conditional element has been always true, (A2) whether each conditional element has been always false, or (A3) whether each conditional element has been both true and false when the conditional statement is satisfied.

A computer readable medium storing a computer program for causing a computer to execute instructions to perform:

• accepting input of a circuit description which describes a circuit by using a plurality of conditional statements each including one or more conditional elements;
• extracting each conditional statement included in the circuit description and each conditional element included in the conditional statements;
• executing the circuit description by using test data for the circuit;
• and
• generating a table including verification information for each conditional statement, the verification information representing (A1) whether each conditional element has been always true, (A2) whether each conditional element has been always false, or (A3) whether each conditional element has been both true and false when the conditional statement is satisfied.