Generating stop indicators during vector processing
AssigneeApple Inc.
InventorsJeffry E. Gonion, Keith E. Diefendorff
Life of this patent
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Abstract
A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more stop indicators corresponding to any detected conflict between the memory addresses, where a given stop indicator indicates a memory hazard. Next, the processor executes the instructions for detecting the conflict between the memory addresses and generating the one or more stop indicators.
Claims30
A method for performing parallel operations in a computer system when one or more memory hazards may be present, comprising:
- receiving instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more stop indicators corresponding to any detected conflict between the memory addresses, wherein a given stop indicator indicates a memory hazard;
- and
- executing the instructions for detecting the conflict between the memory addresses and generating the one or more stop indicators.
A compiler configured to generate instructions based on a feature set of a processor, wherein the processor is configured to:
- receive instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more stop indicators corresponding to any detected conflict between the memory addresses, wherein a given stop indicator indicates a memory hazard;
- and
- execute the instructions for detecting the conflict between the memory addresses and generating the one or more stop indicators.
A computer system configured to execute instructions to avoid one or more memory hazards while performing parallel operations, comprising:
- a processor;
- a memory;
- an instruction fetch unit within the processor configured to fetch:
- instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more stop indicators corresponding to any detected conflict between the memory addresses, wherein a given stop indicator indicates a memory hazard;
- and
- instructions for executing the instructions for detecting the conflict between the memory addresses and generating the one or more stop indicators.
Dependencies are inferred from the claim text.