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AssigneesSeiko Epson Corporation, National University Corporation Nagoya University
InventorsAkinari Todoroki, Akihiko Tamura, Katsuya Tanaka, Hiroaki Takada, Shinya Honda
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To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P1 of the unit processors P0 to P3 comprises an purge inhibit flag 106 for causing the unit processor P1 to enter a lock state where the purge of the task is being inhibited, a hardware semaphore unit 13 for inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor P1 after the unit processor P1 is brought into the lock state, and an interrupt control unit 11 for inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.
A parallel processing device that includes a plurality of unit processors for executing a plurality of tasks in parallel, and achieves exclusive control between one task and another task, and between the task and external interrupt handling when at least one of the plurality of the unit processors receives a request for interrupt handling from the outside, characterized by comprising,
An exclusive control method that includes a plurality of unit processors for executing a plurality of tasks in parallel, and achieves exclusive control between one task and another task, and between the task and an external interrupt handling when at least one of the plurality of the unit processors receives a request for interrupt handling from the outside, characterized by comprising,
An exclusive control method that achieves exclusive control between task processing and external interrupt handling in a processor that includes a plurality of unit processors running in parallel, in which at least one of the plurality of unit processors is capable of performing interrupt handling requested from the outside, characterized by comprising,
Dependencies are inferred from the claim text.