Design structure for an address translation device

A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:

• a system to facilitate communication over an I2C bus between a host device and a slave device, the slave device sharing a common physical address with at least one other slave device on the I2C bus, the system comprising:
• a host device;
• a slave device in communication with the host device over an I2C bus, the slave device sharing a common physical address with at least one other slave device on the I2C bus;
• and
• a translation device intermediate the host device and the slave device and connected to the I2C bus, the translation device comprising:
• a detection module to detect an incoming address on the I2C bus;
• a translation module to translate the incoming address to an outgoing address;
• and
• a communication module to communicate data between the host device and the slave device in response to the outgoing address matching a physical address of the slave device.