Flash/dynamic random access memory field programmable gate array
AssigneeActel Corporation
InventorsJohn McCollum, Vidya Bellippady, Gregory Bakker
Life of this patent
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Abstract
A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
Claims1
A method for interconnecting two nodes in an integrated circuit device comprising:
- storing a charge representing an on-status bit on a gate capacitance of a switching transistor coupled between the two nodes;
- and
- periodically refreshing said charge, wherein periodically refreshing said charge is performed at a periodic interval that is a function of temperature of a die on which said circuit is disposed and comprises periodically coupling a voltage representing said on-status bit to said gate capacitance of said switching transistor through a refresh transistor.
Dependencies are inferred from the claim text.