Phase change memory device using pnp-bjt for preventing change in phase change layer composition and widening bit line sensing margin

A phase change memory device comprising:

• a semiconductor substrate having a plurality of spaced apart bar-shaped active regions which extend in a first direction, wherein the bar-shaped active regions are arranged such that:
• each active region in a pair of active regions is spaced apart from one another by a first interval,
• a pair of active regions is spaced apart from another pair of active regions by a second interval, wherein the four active regions constitute one block, and
• a plurality of blocks are spaced apart from one another by a third interval;
• base regions and emitter regions formed in each active region, wherein the base and emitter regions are alternately formed and are spaced apart from one another;
• lower electrodes formed over the emitter regions, wherein each of the lower electrodes is connected to the respective emitter region;
• a phase change layer and an upper electrode stacked on each of the lower electrodes;
• a plurality of sub bit lines formed over the upper electrodes and extending in second direction that is perpendicular to the first direction, wherein the sub bit lines connect to the corresponding upper electrodes;
• a plurality of word lines formed over the sub bit lines, wherein each word line extends in the second direction and connects to the base regions located on the corresponding active region;
• and
• a plurality of main bit lines formed over the word lines, wherein each main bit line extends in the second direction and connects to the corresponding sub bit line.