Serial Communication Interface with Low Clock Skew

A lane circuit for use in a communication interface comprising:

• a first clock tree terminal adapted to receive a first clock tree signal;
• a second clock tree terminal adapted to receive a second clock tree signal;
• a select terminal adapted to receive a select signal;
• and a multiplexer coupled to the first clock tree terminal, the second clock tree terminal and the select terminal, responsive to the select signal for selecting a clock tree signal from one of the first clock tree terminal and the second clock tree terminal.

A method of generating a clock tree for use in a communication interface comprising the steps of:

• receiving a clock reference signal;
• generating a clock tree signal and a first select signal;
• receiving the clock tree signal and the first select signal in a first lane, the first select signal for selecting a clock signal for an interface circuit;
• propagating the clock tree signal to a second lane and generating a second select signal;
• and receiving the clock tree signal and the second select signal in a second lane, the second select signal for selecting a clock signal for an interface circuit.