Flow and congestion control in switch architectures for multi-hop, memory efficient fabrics
AssigneeFulcrum Microsystems, Inc.
InventorsZhi-Hern Loh, Michael Davies, Uri Cummings
Life of this patent
Estimating the term…
Abstract
A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.
Claims29
A shared memory switch, comprising:
- a plurality of ports configured to receive and transmit frames of data;
- frame classification circuitry configured to classify the frames into a plurality of traffic classes;
- frame memory configured to store the frames, the frame memory including a plurality of shared memory partitions, each of the shared memory partitions corresponding to one or more of the traffic classes, each of the shared memory partitions having a plurality of counters associated therewith, the plurality of counters including at least one per port memory usage counter for each of the plurality of ports and at least one aggregate memory usage counter, the counters associated with each of the shared memory partitions being independent of the counters associated with others of the shared memory partitions;
- and
- congestion management circuitry configured to implement congestion management policies for each of the partitions independently with reference to the counters associated with each of the partitions.
Rate limiting circuitry for use in a shared memory switch having a plurality of input ports for receiving frames of data, the rate limiting circuitry comprising token bucket circuitry implementing a token bucket for each input port, the token bucket circuitry for each port being configured to add tokens to the corresponding token bucket at a specified rate, and to remove tokens from the corresponding token bucket in response to receipt of frames on the corresponding input port, the rate limiting circuitry further comprising pause circuitry configured to enable a pause function for the corresponding input port in response to crossing of a minimum threshold associated with the corresponding token bucket, and to disable the pause function in response to crossing of a pause-off threshold associated with the corresponding token bucket and above the minimum threshold.
A shared memory switch for use in a single-chip fabric or a multi-chip fabric comprising a plurality of shared memory switches, the shared memory switch comprising:
- a plurality of ingress ports and egress ports configured to receive and transmit frames of data;
- frame memory configured to store the frames;
- and
- rate limiting circuitry configured to pause individual ones of the ingress ports in response to usage of the frame memory by the individual ingress ports, the rate limiting circuitry being further configured to pause the individual ingress ports in response to congestion notification information corresponding to one or more of the egress ports or other ones of the shared memory switches in the multi-chip fabric downstream from the shared memory switch.
A shared memory switch for use in a multi-chip fabric comprising a plurality of shared memory switches, comprising:
- a plurality of ports configured to receive and transmit frames of data;
- frame classification circuitry configured to classify the frames into a plurality of traffic classes;
- frame memory configured to store the frames;
- congestion management circuitry configured to generate and transmit class-specific pause frames to selected ones of the ports in response to states of at least some of the plurality of counters;
- and
- egress scheduling circuitry configured to facilitate transmission of the frames, the egress circuitry further being configured to pause transmission of selected ones of the frames corresponding to specific ones of the traffic classes in response to downstream congestion;
- wherein the congestion management circuitry and the egress scheduling circuitry together enable implementation of a congestion management domain encompassing the plurality of shared memory switches.
A shared memory switch for use in a multi-chip fabric comprising a plurality of shared memory switches, the shared memory switch comprising:
- a plurality of ingress ports and egress ports configured to receive and transmit frames of data, each of the frames comprising one or more segments;
- frame memory configured to store the frames;
- a scheduler configured to allocate and de-allocate space in the frame memory for storage of the frames on a segment-by segment basis, the scheduler being further configured to generate memory allocation status information on a segment-by-segment basis;
- a low latency status channel configured to communicate the memory allocation status information on a segment-by-segment basis;
- a frame processing pipeline configured to provide frame-level processing of the frames in parallel with the scheduler and frame memory and with reference to headers associated with the frames, the frame processing pipeline being further configured to maintain port information for each frame identifying one of the ingress ports on which the frame was received and at least one of the egress ports on which the frame is to be transmitted, the frame processing pipeline being further configured to receive the memory allocation status information from the scheduler via the status channel and to correlate the memory allocation status information with the port information;
- and
- congestion management circuitry configured to effect at least one policy with reference to the correlated memory allocation status and port information.
A shared memory switch for use in a multi-chip fabric comprising a plurality of shared memory switches, the shared memory switch comprising:
- a plurality of ingress ports and egress ports configured to receive and transmit frames of data;
- frame memory configured to store the frames;
- and
- congestion management circuitry configured to detect congestion associated with a particular one of the egress ports, identify a flow with reference to a frame directed to the particular egress port, and generate a first congestion notification message directed to an upstream one of the shared memory switches in the multi-chip fabric from which the flow originated, the congestion management circuitry being further configured to pause a particular one of the ingress ports for a period of time in response to a second congestion notification message received from a downstream one of the shared memory switches in the multi-chip fabric, and automatically unpause the particular ingress port without a subsequent congestion notification message from the downstream shared memory switch, wherein the congestion management circuitry is further configured to exponentially increase the period of time in response to a third congestion notification message from the downstream shared memory switch.
A shared memory switch for use in a multi-chip fabric comprising a plurality of shared memory switches, the shared memory switch comprising:
- a plurality of ingress ports and egress ports configured to receive and transmit frames of data;
- frame memory configured to store the frames;
- and
- congestion management circuitry configured to detect congestion associated with a particular one of the egress ports, generate a first multi-cast congestion notification message directed to a subset of ingress ports of the shared memory switches upstream in the multi-chip fabric and associated with a first flow directed to the particular egress port and an associated priority to thereby facilitate pausing of the first flow, and generate a second multi-cast congestion notification message directed to the subset of ingress ports to thereby facilitate unpausing of the first flow, the congestion management circuitry being further configured to, in response to a third multi-cast congestion notification message received from a downstream one of the shared memory switches, pause a second flow associated with a particular one of the ingress ports and directed to a particular egress port associated with the downstream shared memory switch and an associated priority, and unpause the second flow in response to a fourth multi-cast congestion notification message from the downstream shared memory switch.
Dependencies are inferred from the claim text.