Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorNaoki Yamada
Life of this patent
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Abstract
According to the present invention, an intra-macro match determining circuit 111 internally determines whether or not n test outputs from each macro all have the same level. The result of the determination is combined with some of the test outputs, and the resultant signal is output to a tester. Thus, the determination result for a match is combined with the test outputs instead of a particular value. Consequently, the same expected value can also be used for individual macro testing, and output bits are assigned to each of the macros. Therefore, in internally performing a comparison with the expected value, the tester can easily detect defective macros.
Claims17
A semiconductor device comprising:
- a plurality of memory macros;
- and
- an intra-macro match determining unit outputting an intra-macro match signal corresponding to at least one of the plurality of memory macros and comparing test output data from the memory macro to determine whether or not the test output data match, the intra-macro match determining unit outputting some of the test output data from the memory macro as an output level determination signal used to determine level of the match,
- wherein a logic of the intra-macro match signal is determined on a basis of a logic of the output level determination signal according to a state of the match between the test output data from the memory macro.
Dependencies are inferred from the claim text.