Redundancy architecture for an integrated circuit memory

An integrated circuit memory comprising:

• a plurality of memory bank means forming a repair group of memory bank means, each of said plurality of memory bank means having an array of memory cell means and a plurality of bit lines coupled to respective columns of memory cell means and not shared with any other memory bank means;
• wherein
• at least one of said plurality of memory bank means includes at least one redundant row of memory cell means and at least one non-redundant row of memory cell means;
• and further comprising:
• redundant row control means coupled to said plurality of memory bank means and responsive to input memory address signals addressing a defective row of memory cell means within any memory bank means within said repair group for substituting one of said at least one redundant rows of memory cell means for said defective row of memory cell means.

An integrated circuit memory comprising:

• an array of memory cells having a plurality of columns of memory cells, including at least one redundant column of memory cells, and a plurality of bit lines, each of said plurality of bit lines being coupled to one of said columns;
• multiplexing circuitry coupled to said plurality of bit lines to group said plurality of bit lines into bit groups having a multiplexer width number of bit lines and responsive to an input memory address to select a bit line from each bit group to carry a signal for a corresponding data bit within a data word to be accesses;
• redundant column control circuitry coupled to said multiplexing circuitry and responsive to a defect signal indicative of a location of a defective column of memory cells within said array of memory cells to control said multiplexing circuitry to select said bit lines to form said bit groups such that:
• a set of bit lines forming a bit group that would otherwise include a bit line of said defective column instead includes one or more bit lines to one side of said defective column toward said at least one redundant column and taken from positions shifted by a shift number of bit lines, said defective column thereby being omitted from said set of bit lines and said shift number being less than said multiplexer size number;
• any other bit group to said one side comprises a selection of bit lines correspondingly shifted by said shift number compared to when said defective column is not present;
• and
• at least one of said bit groups extending to said one side includes at least one of said at least one redundant columns.

An integrated circuit memory comprising:

• an array of memory cell means having a plurality of columns of memory cell means, including at least one redundant column of memory cell means, and a plurality of bit lines, each of said plurality of bit lines being coupled to one of said columns;
• multiplexing means coupled to said plurality of bit lines for grouping said plurality of bit lines into bit groups having a multiplexer width number of bit lines and, in response to an input memory address, for selecting a bit line from each bit group to carry a signal for a corresponding data bit within a data word to be accesses;
• redundant column control means coupled to said multiplexing circuitry and responsive to a defect signal indicative of a location of a defective column of memory cells within said array of memory cells for controlling said multiplexing means to select said bit lines to form said bit groups such that:
• a set of bit lines forming a bit group that would otherwise include a bit line of said defective column instead includes one or more bit lines to one side of said defective column toward said at least one redundant column and taken from positions shifted by a shift number of bit lines, said defective column thereby being omitted from said set of bit lines and said shift number being less than said multiplexer size number;
• any other bit group to said one side comprises a selection of bit lines correspondingly shifted by said shift number compared to when said defective column is not present;
• and
• at least one of said bit groups extending to said one side includes at least one of said at least one redundant columns.

A method of operating an integrated circuit memory having an array of memory cells containing a plurality of columns of memory cells, including at least one redundant column of memory cells, and a plurality of bit lines, each of said plurality of bit lines being coupled to one of said columns, said method comprising the steps of:

• grouping said plurality of bit lines into bit groups having a multiplexer width number of bit lines;
• in response to an input memory address, selecting a bit line from each bit group to carry a signal for a corresponding data bit within a data word to be accesses;
• in response to a defect signal indicative of a location of a defective column of memory cells within said array of memory cells controlling said step of selecting said bit lines to form said bit groups such that:
• a set of bit lines forming a bit group that would otherwise include a bit line of said defective column instead includes one or more bit lines to one side of said defective column toward said at least one redundant column and taken from positions shifted by a shift number of bit lines, said defective column thereby being omitted from said set of bit lines and said shift number being less than said multiplexer size number;
• any other bit group to said one side comprises a selection of bit lines correspondingly shifted by said shift number compared to when said defective column is not present;
• and
• at least one of said bit groups extending to said one side includes at least one of said at least one redundant columns.