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US 2008/0259693 A1Published application
Semiconductor Device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsMunehiro Kozuma, Yoshiyuki Kurokawa
Life of this patent
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Abstract
A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed.
Claims21
A semiconductor device comprising:
- a memory circuit;
- and
- a central processing unit configured to execute a program based on potential stored in the memory circuit,
- wherein the memory circuit includes:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, either high or low potential is stored in each of the memory cells,
- wherein the high potential is stored in a first plural number of the memory cells, and the low potential is stored in a second plural number of the memory cells,
- wherein a semiconductor element is connected to one of the word lines and one of the bit lines, at one of the memory cells of less number of the first plural number and the second plural number, and
- wherein a vacant cell is consisted of one of the word lines and one of the bit lines, at one of the memory cells of larger number of the first plural number and the second plural number.
8 more elements
A semiconductor device comprising:
- a memory circuit;
- and
- a dedicated circuit configured to execute an arithmetic operation based on data stored in the memory circuit,
- wherein the memory circuit includes:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, either high or low potential is stored in each of the memory cells,
- wherein the high potential is stored in a first plural number of the memory cells, and the low potential is stored in a second plural number of the memory cells,
- wherein a semiconductor element is connected to one of the word lines and one of the bit lines, at one of the memory cells of less number of the first plural number and the second plural number, and
- wherein a vacant cell is consisted of one of the word lines and one of the bit lines, at one of the memory cells of larger number of the first plural number and the second plural number.
8 more elements
A semiconductor device comprising:
- a memory circuit;
- a central processing unit configured to execute a program based on potential stored in the memory circuit;
- and
- a dedicated circuit configured to execute an arithmetic operation based on data stored in the memory circuit,
- wherein the memory circuit includes:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, either high or low potential is stored in each of the memory cells,
- wherein the high potential is stored in a first plural number of the memory cells, and the low potential is stored in a second plural number of the memory cells,
- wherein a semiconductor element is connected to one of the word lines and one of the bit lines, at one of the memory cells of less number of the first plural number and the second plural number, and
- wherein a vacant cell is consisted of one of the word lines and one of the bit lines, at one of the memory cells of larger number of the first plural number and the second plural number.
9 more elements
A semiconductor device comprising:
- a memory circuit;
- and
- a central processing unit configured to execute a program based on potential stored in the memory circuit,
- wherein the memory circuit includes:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, and
- wherein the memory circuit includes at least one of the word lines intersecting memory cells in which a semiconductor element is not provided.
6 more elements
A semiconductor device comprising:
- a memory circuit;
- and
- a dedicated circuit configured to execute an arithmetic operation based on data stored in the memory circuit,
- wherein the memory circuit includes:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, and
- wherein the memory circuit includes at least one of the word lines intersecting memory cells in which a semiconductor element is not provided.
6 more elements
A semiconductor device comprising:
- a memory circuit;
- a central processing unit configured to execute a program based on potential stored in the memory circuit;
- and
- a dedicated circuit configured to execute an arithmetic operation based on data stored in the memory circuit,
- wherein the memory circuit includes:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, and
- wherein the memory circuit includes at least one of the word lines intersecting memory cells in which a semiconductor element is not provided.
7 more elements
Dependencies are inferred from the claim text.