Non-volatile memory device, memory system, and lsb read method
AssigneeSamsung Electronics Co., Ltd.
InventorSang-won HWANG
Life of this patent
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Abstract
A non-volatile memory device and system as well as a LSB read method are disclosed. The LSB read method includes reading LSB data from a memory cell during a main LSB read operation making reference to a flag cell threshold voltage, determining whether the LSB data contains an error, and if the LSB data contains an error re-reading the LSB data during a LSB recover-read operation without making reference to the flag cell threshold voltage.
Claims20
A Least Significant Bit (LSB) read method for a non-volatile memory device comprising multi-level memory cells, the method comprising:
- reading LSB data from a memory cell during a main LSB read operation making reference to a flag cell threshold voltage;
- determining whether the LSB data contains an error;
- and
- if the LSB data contains an error re-reading the LSB data during a LSB recover-read operation without making reference to the flag cell threshold voltage.
A non-volatile memory device comprising:
- a memory core comprising a memory cell capable of being programmed by a LSB program operation and a MSB program operation;
- a read state machine configured to control the memory core to perform the LSB read operation or the MSB read operation in relation to an externally applied input read command and corresponding address and with reference to a flag cell threshold voltage;
- an error detect module configured to detect whether LSB data read from the memory cell during a main LSB read operation contain an error and generating an error signal upon detecting the error;
- and
- an LSB recover-read state machine responsive to the error signal and configured to control the memory core to perform a LSB recover-read operation operating without reference to the flag cell threshold voltage.
A memory system comprising:
- a non-volatile memory device controlled by a memory controller,
- wherein the non-volatile memory device comprises a memory core comprising a memory cell capable of being programmed by a LSB program operation and a MSB program operation;
- and
- the operative combination of the non-volatile memory device and the memory controller implement;
- a read state machine configured to control the memory core to perform the LSB read operation or the MSB read operation in relation to an externally applied input read command and corresponding address and with reference to a flag cell threshold voltage;
- an error detect module configured to detect whether LSB data read from the memory cell during a main LSB read operation contain an error and generating an error signal upon detecting the error;
- and
- an LSB recover-read state machine responsive to the error signal and configured to control the memory core to perform a LSB recover-read operation operating without reference to the flag cell threshold voltage.
Dependencies are inferred from the claim text.