US 2008/0259683 A1 · METHOD AND CIRCUIT FOR PROGRAMMING A MEMORY CELL, IN PARTICULAR OF THE NOR FLASH TYPE

Abstract

A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.

Claims28

Dependent claims

A programming method, comprising:

applying a continuous voltage to a drain terminal of a memory cell and a suitable programming voltage signal to a gate terminal of the memory cell;
applying a constant voltage to said gate terminal and regulating a voltage of said drain terminal while the constant voltage is applied to the gate terminal;
the regulating including maintaining the voltage of said drain terminal substantially at a fixed value until a threshold voltage value of said memory cell reaches a desired threshold voltage level;
and
stopping the regulating in response to detecting that a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the threshold voltage of said memory cell reaching said desired threshold voltage level.

2 more elements

A programming circuit of a memory cell, comprising:

a selection circuit having a terminal for coupling to the memory cell;
a regulation transistor positioned between a first voltage reference and the selection circuit, said regulation transistor and said selection circuit being interconnected at a first inner circuit node;
a first voltage comparator having a first input terminal, a second input terminal feedback coupled to said first inner circuit node, and an output terminal coupled to a gate terminal of said regulation transistor;
a first reference circuit having an output terminal and structured to provide a first reference gate voltage value;
and
a second voltage comparator having a first input terminal coupled to the reference circuit, a second input terminal feedback coupled to said output terminal of said first voltage comparator, and an output terminal coupled to an enable terminal of said first voltage comparator.

3 more elements

A memory device, comprising:

a memory cell;
and
a programming circuit coupled to the memory cell and structured to program the memory cell, the programming circuit including:
a selection circuit having a terminal for coupling to the memory cell;
a regulation transistor positioned between a first voltage reference and the selection circuit, said regulation transistor and said selection circuit being interconnected at a first inner circuit node;
a first voltage comparator having a first input terminal, a second input terminal feedback coupled to said first inner circuit node, and an output terminal coupled to a gate terminal of said regulation transistor;
a first reference circuit having an output terminal and structured to provide a first reference gate voltage value;
and
a second voltage comparator having a first input terminal coupled to the reference circuit, a second input terminal feedback coupled to said output terminal of said first voltage comparator, and an output terminal coupled to an enable terminal of said first voltage comparator.

6 more elements

Dependencies are inferred from the claim text.

Method and circuit for programming a memory cell, in particular of the nor flash type

Life of this patent

Method and circuit for programming a memory cell, in particular of the nor flash type

Life of this patent

Abstract

Claims28