Layout structure of bit line sense amplifiers for a semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Sun Min, Kyu-Chan Lee, Chul-Woo Yi, Jong-Hyun Choi
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Abstract
A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
Claims16
A layout structure of bit line sense amplifiers for use in a semiconductor memory device, the layout structure comprising:
- first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors;
- wherein each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
A layout structure of bit line sense amplifiers for use in a semiconductor memory device, the layout structure comprising first and second bit line sense amplifiers electrically controlled by a first column selection line signal, the first and second bit line sense amplifiers being arranged such that the first and second bit line sense amplifiers are not adjacent along a column.
A semiconductor memory device, comprising:
- a plurality of transistors arranged to form first and second bit line sense amplifiers;
- and
- a first column selection line coupled to the first and second bit line amplifiers,
- wherein an active region of any transistor of the first bit line sense amplifier is separate from an active region of any transistor of the second bit line sense amplifier.
A layout method of bit line sense amplifiers for use in a semiconductor memory device, the method comprising:
- arranging adjacent transistors in different bit line sense amplifiers controlled by a common selection line signal to be separate;
- and
- arranging adjacent transistors in different bit line sense amplifiers controlled by different selection line signals to share a portion of an active region.
Dependencies are inferred from the claim text.