Digital Single Event Transient Hardened Register Using Adaptive Hold
AssigneeHoneywell International Inc.
InventorsRoy M. Carlson, David O. Erstad
Life of this patent
Estimating the term…
Abstract
By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.
Claims19
A method for mitigating against effects of Digital Single Event Transient (DSET), comprising:
- detecting that a data input to a data storage element has a first transition from a first state to a second state;
- determining whether the first transition occurs prior to a capturing clock edge;
- if the first transition occurs within a time period prior to the capturing clock edge, delaying the capturing clock edge;
- determining whether the data input has a second transition from the second state to the first state within the time period after the first transition;
- and
- if the data input has the second transition within a time period after the first transition, capturing the first state.
A system for mitigating against the effects of Digital Single Event Transient (DSET), comprising in combination:
- a data storage element operable to latch data based on a clock input;
- and
- a clock circuit that controls the clock input to the data storage element, wherein the clock circuit increases a hold time of the data storage element by a time period after a transient pulse occurs on a data input to the data storage element so as to delay when the data storage element latches data.
A system for mitigating against the effects of Digital Single Event Transient (DSET), comprising in combination:
- a data storage element operable to latch data based on two clock signals;
- a delay circuit that receives and inverts a first data input to provide a second data input, wherein the delay circuit delays providing the second data input by a time period;
- and
- a clock circuit that receives the first data input, the second data input, and a clock input and provides as an output two clock outputs that control the two clock signals, wherein the clock circuit increases a hold time of the data storage element by the time period after a transient pulse occurs on a data input to the data storage element.
Dependencies are inferred from the claim text.