Clock regeneration circuit
AssigneeOki Electric Industry Co., Ltd.
InventorsHideaki Tamai, Masayuki Kashima
Life of this patent
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Abstract
A clock regeneration circuit includes a half-bit delay device that outputs a half-bit delayed signal B of a multi-level input signal A, a one-bit delay device that outputs a one-bit delayed signal C of the signal A, an adder, an attenuator that forms an threshold signal, an XOR circuit, and a BPF that outputs a clock signal with a frequency corresponding to a bit rate of the XOR signal. The XOR signal is calculated as an XOR of a two-level input signal F, which is a logical zero when a level of the signal A is no more than a level of the threshold signal and otherwise is a logical one, and a two-level input signal G, which is a logical zero when a level of the signal B is no more than the level of the threshold signal and otherwise is a logical one.
Claims6
A clock regeneration circuit at which a multi-level input signal of a predetermined period, with at least two signal levels, is inputted and which outputs a clock signal synchronized with the predetermined period, the clock regeneration circuit comprising:
- a first delay device that delays the multi-level input signal by a duration shorter than a one-bit length of the multi-level input signal and outputs a first multi-level delayed signal;
- a second delay device that delays the multi-level input signal by a duration of the one-bit length of the multi-level input signal and outputs a second multi-level delayed signal;
- an adder that adds the second multi-level delayed signal with the multi-level input signal and outputs an added signal;
- an attenuator that attenuates the added signal and outputs a threshold signal;
- an exclusive or circuit, at which the multi-level input signal, the first multi-level delayed signal and the threshold signal are inputted, that calculates an exclusive or of
- (a) a two-level input signal which is at a logical zero when a level of the multi-level input signal is less than or equal to a level of the threshold signal and is at a logical one when the level of the multi-level input signal is higher than the level of the threshold signal and
- (b) a two-level delayed signal which is at a logical zero when a level of the first multi-level delayed signal is less than or equal to the level of the threshold signal and is at a logical one when the level of the first multi-level delayed signal is higher than the level of the threshold signal,
- and outputs a result of this calculation as an exclusive or signal;
- and
- a clock regeneration element that outputs the clock signal with a frequency corresponding to a bit rate of the exclusive or signal.
Dependencies are inferred from the claim text.