Clock signal networks for structured asic devices
AssigneeAltera Corporation
InventorsChooi Pei Lim, Joo Ming Too, Yew Fatt (Edwin) Kok, Kar Keng Chua
Life of this patent
Estimating the term…
Abstract
Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.
Claims1
Clock distribution circuitry for an integrated comprising:
- a deterministic portion and configurable portions, where each of the configurable portions is associated with a respective one of predetermined locations that are spaced from one another and distributes a clock signal received from the deterministic portion at the associated predetermined location to clock utilization circuitry within a predetermined area adjacent to the associated predetermined location, where logic elements on the integrated circuit are operable to provide buffer circuits for the clock utilization circuitry and logic functions when not providing the buffer circuits.
Dependencies are inferred from the claim text.